參數(shù)資料
型號: ADUC7121BBCZ
廠商: Analog Devices Inc
文件頁數(shù): 47/96頁
文件大?。?/td> 0K
描述: IC ARM7TDMI MCU 126KB 108CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -10°C ~ 95°C
封裝/外殼: 108-LFBGA,CSPBGA
包裝: 托盤
Data Sheet
ADuC7121
Rev. B | Page 51 of 96
In H-bridge mode, HMODE = 1 and Table 71 determine the
PWM outputs, as listed in Table 72.
Table 72. PWM Output Selection
PWMCOM1 MMR
PWM Outputs
ENA
HOFF
POINV
DIR
PWM1
PWM2
PWMR3
PWM4
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1 HS is high side, LS is low side, X is a don’t care bit.
On power-up, PWMCON1 defaults to 0x12 (HOFF = 1 and
HMODE = 1). All GPIO pins associated with the PWM are
configured in PWM mode by default (see Table 73).
Table 73. Compare Register (Default Value = 0x0000, Access
is Read/Write)
Name
Address
Default Value
Access
PWM1COM1
0xFFFF0F84
0x0000
R/W
PWM1COM2
0xFFFF0F88
0x0000
R/W
PWM1COM3
0xFFFF0F8C
0x0000
R/W
PWM2COM1
0xFFFF0F94
0x0000
R/W
PWM2COM2
0xFFFF0F98
0x0000
R/W
PWM2COM3
0xFFFF0F9C
0x0000
R/W
PWM3COM1
0xFFFF0FA4
0x0000
R/W
PWM3COM2
0xFFFF0FA8
0x0000
R/W
PWM3COM3
0xFFFF0FAC
0x0000
R/W
The PWM trip interrupt can be cleared by writing any value to
the PWMICLR MMR. Note that when using the PWM trip inter-
rupt, users should make sure that the PWM interrupt has been
cleared before exiting the ISR. This prevents generation of multiple
interrupts.
PWM CONVERT START CONTROL
The PWM can be configured to generate an ADC convert start
signal after the active low side signal goes high. There is a
programmable delay between when the low-side signal goes
high and the convert start signal is generated.
This is controlled via the PWMCON2 MMR. If the delay
selected is higher than the width of the PWM pulse, the
interrupt remains low.
Table 74. PWMCON2 MMR Bit Designations (Address =
0xFFFF0FB4, Default Value = 0x00)
Bit
Name
Value
Description
7
CSEN
Set to 1 by the user to enable the PWM
to generate a convert start signal.
Cleared by the user to disable the PWM
convert start signal.
3:0
CSD3
to
CSD0
Convert start delay. Delays the convert
start signal by a number of clock
pulses.
0000
4 clock pulses.
0001
8 clock pulses.
0010
12 clock pulses.
0011
16 clock pulses.
0100
20 clock pulses.
0101
24 clock pulses.
0110
28 clock pulses.
0111
32 clock pulses.
1000
36 clock pulses.
1001
40 clock pulses.
1010
44 clock pulses.
1011
48 clock pulses.
1100
52 clock pulses.
1101
56 clock pulses.
1110
60 clock pulses.
1111
64 clock pulses.
When calculating the time from the convert start delay to the
start of an ADC conversion, the user needs to take account of
internal delays. The following example shows the case for a
delay of four clocks. One additional clock is required to pass the
convert start signal to the ADC logic. When the ADC logic
receives the convert start signal, an ADC conversion begins on
the next ADC clock edge (see Figure 35).
Figure 35. ADC Conversion
UCLOCK
LOW SIDE
COUNT
PWM SIGNAL
SIGNAL PASSED
TO ADC LOGIC
09
49
2-
03
4
TO CONVST
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