參數(shù)資料
型號： ADUC7121BBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/96頁
文件大小： 0K
描述： IC ARM7TDMI MCU 126KB 108CSPBGA
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 9x12b，D/A 4x12b
振蕩器型： 內部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 托盤
ADuC7121
Data Sheet
Rev. B | Page 38 of 96
Bit
Description
1
Command fail.
Set automatically when a command completes
unsuccessfully.
Cleared automatically when reading FEExSTA register.
0
Command complete.
Set by MicroConverter when a command is complete.
Cleared automatically when reading FEExSTA register.
FEE0MOD Register
Name:
FEE0MOD
Address:
0xFFFF0E04
Default value:
0x80
Access:
Read and write
FEE1MOD Register
Name:
FEE1MOD
Address:
0xFFFF0E84
Default value:
0x80
Access:
Read and write
Table 44. FEExMOD MMR Bit Designations
Bit
Description
7:5
Reserved. These bits are always set to 0 except when
writing keys. See the Sequence to Write the Key to
Protection Registers section for details.
4
Flash/EE interrupt enable.
Set by the user to enable the Flash/EE interrupt. The
interrupt occurs when a command is complete.
Cleared by the user to disable the Flash/EE interrupt.
3
Erase/write command protection.
Set by the user to enable the erase and write commands.
Cleared to protect the Flash/EE memory against
erase/write command.
2
Reserved. The user must set this bit to 0.
1:0
Flash/EE wait states. Both Flash/EE blocks must have the
same wait state value for any change to take effect.
FEE0CON Register
Name:
FEE0CON
Address:
0xFFFF0E08
Default value:
0x00
Access:
Read and write
FEE1CON Register
Name:
FEE1CON
Address:
0xFFFF0E88
Default value:
0x00
Access:
Read and write
Table 45. Command Codes in FEExCON
Code
Command
Description
0x001
Null
Idle state.
0x011
Single read
Load FEExDAT with the 16-bit data indexed by FEExADR.
0x021
Single write
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 s.
0x031
Erase/write
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms.
0x041
Single verify
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is
returned in FEExSTA Bit 1.
0x051
Single erase
Erase the page indexed by FEExADR.
0x061
Mass erase
Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction.
0x07
Reserved
Reserved.
0x08
Reserved
Reserved.
0x09
Reserved
Reserved.
0x0A
Reserved
Reserved.
0x0B
Signature
Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.
0x0C
Protect
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06)
or with the key.
0x0D
Reserved
Reserved.
0x0E
Reserved
Reserved.
0x0F
Ping
No operation, interrupt generated.
1
The FEExCON register always reads 0x07 immediately after execution of any of these commands.
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