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參數資料
| 型號： | ADUC7036CCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 75/132頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數據轉換器： | A/D 2x16b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7036
Rev. C | Page 47 of 132
ADC Interrupt Mask Register
Name: ADCMSKI
Address: 0xFFFF0504
Default Value: 0x00
Access: Read/write
Function: This register allows the ADC interrupt sources to be individually enabled. The bit positions in this register are the same as the
lower eight bits in the ADCSTA MMR. If a bit is set by user code to 1, the respective interrupt is enabled. By default, all bits are 0,
meaning all ADC interrupt sources are disabled.
ADC Mode Register
Name: ADCMDE
Address: 0xFFFF0508
Default Value: 0x00
Access: Read/write
Function: This 8-bit register configures the mode of operation of the ADC subsystem.
Table 36. ADCMDE MMR Bit Designations
Bit
Description
7
Not used. This bit is reserved for future functionality and should be written as 0 by user code.
6
20 kΩ resistor select.
Set to 1 to select the 20 kΩ resistor as shown in Figure 21.
Set to 0 to select the direct path to ground as shown in Figure 21 (default).
5
Low power mode reference select.
Set to 1 to enable the precision voltage reference in either low power mode or low power plus mode, thereby increasing current
consumption.
Set to 0 to enable the low power voltage reference in either low power mode or low power plus mode (default).
4 to 3
ADC power mode configuration.
00 = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum electrical performance.
01 = ADC low power mode. If enabled, the I-ADC operates with reduced current consumption. This limitation in current
consumption is achieved (at the expense of ADC noise performance) by fixing the gain to 128 and using the on-chip low power
(131 kHz) oscillator to directly drive the ADC circuits.
10 = ADC low power plus mode. If enabled, the ADC operates with reduced current consumption. In this mode, the gain is fixed to
512 and the current consumed is approximately 200 μA more than the ADC low power mode. The additional current consumed
also ensures that the ADC noise performance is better than that achieved in ADC low power mode.
11 = not defined.
2 to 0
ADC operation mode configuration.
000 = ADC power-down mode. All ADC circuits (including internal reference) are powered down.
001 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts.
010 = ADC single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC enters idle mode when
the single shot conversion is complete. A single conversion takes two to three ADC clock cycles depending on the chop mode.
011 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset.
100 = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using an internally
generated 0 V. The calibration is carried out at the user programmed ADC settings; therefore, as with a normal single ADC
conversion, it takes two to three ADC conversion cycles before a fully settled calibration result is ready. The calibration result is
automatically written to the ADCxOF MMR of the respective ADC. The ADC returns to idle mode and the calibration and
conversion ready status bits are set at the end of an offset calibration cycle.
101 = ADC self-gain calibration. In this mode, a gain calibration against an internal reference voltage is performed on all enabled
ADCs. A gain calibration is a two-stage process and takes twice the time of an offset calibration. The calibration result is
automatically written to the ADCxGN MMR of the respective ADC. The ADC returns to idle mode, and the calibration and
conversion ready status bits are set at the end of a gain calibration cycle. An ADC self-gain calibration should only be carried out
on the current channel ADC. Preprogrammed, factory calibration coefficients (downloaded automatically from internal Flash/EE)
should be used for voltage temperature measurements. If an external NTC is used, an ADC self-calibration should be performed
on the temperature channel.
110 = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC channels against an
external zero-scale voltage driven at the ADC input pins. The calibration is carried out at the user programmed ADC settings;
therefore, as with a normal, single ADC conversion, it takes three ADC conversion cycles before a fully settled calibration result is ready.
111 = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC channels against an
external full-scale voltage driven at the ADC input pins.
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