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| 型號： | ADUC7036CCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 58/132頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 96K FLASH DUAL 48LFCSP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設備： | PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉換器： | A/D 2x16b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7036
Rev. C | Page 31 of 132
FLASH/EE MEMORY RELIABILITY
The Flash/EE memory array on the part is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as initial page erase sequence, read/verify
sequence, byte program sequence, and second read/verify
sequence.
In reliability qualification, every halfword (16-bit wide) location
of the three pages (top, middle, and bottom) in the Flash/EE
memory is cycled 10,000 times from 0x0000 to 0xFFFF. As shown
in Table 1, the Flash/EE memory endurance qualification of the
part is carried out in accordance with JEDEC Retention Lifetime
Specification A117. The results allow the specification of a
minimum endurance figure over supply and temperature of
10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the part is
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. In addition, note that
retention lifetime, based on an activation energy of 0.6 eV, derates
0
150
300
450
600
25
40
55
70
85
100
115
130
145
RE
T
E
NT
IO
N
(
Y
ea
rs
)
JUNCTION TEMPERATURE (°C)
07
47
4-
01
4
Figure 14. Flash/EE Memory Data Retention
CODE EXECUTION TIME FROM SRAM AND FLASH/EE
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns, and a clock cycle is 49 ns
minimum. However, when the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM. If the data is in Flash/EE, two cycles must be
added: one cycle to execute the instruction and two cycles to
retrieve the 32-bit data from Flash/EE. A control flow instruction,
such as a branch instruction, takes one cycle to fetch and two
cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
In Thumb mode, where instructions are 16 bits, one cycle is
needed to fetch any instruction.
In ARM mode, with CD = 0, two cycles are needed to fetch the
32-bit instructions. With CD > 0, no extra cycles are required
for the fetch because the Flash/EE memory continues to be
clocked at full speed. In addition, some dead time is needed
before accessing data for any value of CD bits.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is needed
to decode the new address of the program counter, and then
four cycles are needed to fill the pipeline if CD = 0.
A data processing instruction involving only the core register
does not require any extra clock cycles. Data transfer instructions
are more complex and are summarized in Table 18.
Table 18. Typical Execution Cycles in ARM/Thumb Mode
Instructions
Fetch Cycles
Dead Time
Data Access
LD
2/1
1
2
LDH
2/1
1
LDM/PUSH
2/1
N
2 × N
STR
2/1
1
2 × 50 μs
STRH
2/1
1
50 μs
STRM/POP
2/1
N
2 × N × 50 μs
With 1 < N ≤ 16, N is the number of data to load or store in the
multiple load/store instruction.
By default, Flash/EE code execution is suspended during any
Flash/EE erase or write cycle. A page (512 bytes) erase cycle takes
20 ms and a write (16 bits) word command takes 50 μs. However,
the Flash/EE controller allows erase/write cycles to be aborted
if the ARM core receives an enabled interrupt during the current
Flash/EE erase/write cycle. The ARM7 can, therefore, imme-
diately service the interrupt and then return to repeat the Flash/EE
command. The abort operation typically requires 10 clock cycles.
If the abort operation is not feasible, the user can run Flash/EE
programming code and the relevant interrupt routines from
SRAM, allowing the core to immediately service the interrupt.
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