參數(shù)資料
型號(hào)： ADSP-TS203S
廠商： Analog Devices, Inc.
英文描述： TigerSHARC Embedded Processor
中文描述： TigerSHARC系列嵌入式處理器
文件頁數(shù)： 21/40頁
文件大小： 609K
代理商： ADSP-TS203S
ADSP-TS203S
Preliminary Technical Data
Rev. PrB
|
Page 21 of 40
|
December 2003
ADSP-TS203S—SPECIFICATIONS
Note that component specifications are subject to change with-
out notice. For information on Link port electrical
characteristics, see
Link Port Low-Voltage, Differential-Signal
(LVDS) Electrical Characteristics and Timing on page 27
.
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Parameter
V
DD
V
DD_A
V
DD_IO
V
DD_DRAM
T
CASE
V
IH
V
IL
I
DD
I
DD_A
I
DD_IO
Test Conditions
Min
0.95
0.95
2.38
1.425
–40
1.7
–0.5
Typ
Max
1.05
1.05
2.63
1.575 V
+85
3.63
0.8
Unit
V
V
V
Internal Supply Voltage
Analog Supply Voltage
I/O Supply Voltage
Internal DRAM Supply Voltage
Case Operating Temperature
High-Level Input Voltage
1
Low-Level Input Voltage
1
V
DD
supply current for typical activity
2
V
DD_A
supply current for typical activity
V
DD_IO
supply current for typical activity
2
(DRAM
Internal Regulator Disabled)
V
DD_DRAM
supply current for typical activity
2,3
°C
V
V
A
mA
A
1
Applies to input and bidirectional pins.
2
For details on internal and external power calculation issues, see the
EE-170, Estimating Power for the ADSP-TS201S
on the Analog Devices website.
3
For ENEDREG=1, the internal DRAM supply is used; there is no I
DD_DRAM
for this condition.
4
If the clock driver voltage is > 2.8 V and the clock driver voltage is used to generate SCLK_V
REF
, this formula becomes: (V
CLOCK_DRIVE
/2) ±5%)
@ V
DD
, V
DD_IO
= max
@ V
DD
, V
DD_IO
= min
@ CCLK=500 MHz, V
DD
=1.0 V, T
CASE
=25oC
@ CCLK=500 MHz, V
DD
=1.0 V, T
CASE
=25oC
@ SCLK=100 MHz, V
DD_IO
=2.5 V, T
CASE
=25oC,
ENEDREG=0
@ CCLK=500 MHz, V
DD_DRAM
=1.5 V,
T
CASE
=25oC, ENEDREG=0
2.39
20
0.16
50
I
DD_DRAM
0.40
A
V
REF
SCLK_V
REF
Voltage reference
Voltage reference
(V
DD_IO
×
0.56)
4
(V
DD_IO
×
0.56)
4
V
V
Parameter
V
OH
V
OL
I
IH
I
IH_PU
I
IH_PD
I
IL
I
IL_PU
I
IL_PU_AD
I
OZH
I
OZH_PD
I
OZL
I
OZL_PU
I
OZL_PU_AD
I
OZL_OD
C
IN
Parameter name suffix conventions: no suffix = applies to pins without pullup or pull down resistors,
_PD
= applies to pin types (pd) or
(pd_0),
_PU
= applies to pin types (pu) or (pu_0),
_PU_AD
= applies to pin types (pu_ad),
_OD
= applies to pin types OD
Test Conditions
@V
DD_IO
=min, I
OH
= –2 mA
@V
DD_IO
=min, I
OL
=4 mA
@V
DD_IO
=max, V
IN
=V
DD_IO
max
@V
DD_IO
=max, V
IN
=V
DD_IO
max
@V
DD_IO
=max, V
IN
=V
DD_IO
max
@V
DD_IO
=max, V
IN
=0V
@V
DD_IO
=max, V
IN
=0V
@V
DD_IO
=max, V
IN
=0V
@V
DD_IO
=max, V
IN
=V
DD_IO
max
@V
DD_IO
=max, V
IN
=V
DD_IO
max
@V
DD_IO
=max, V
IN
=0V
@V
DD_IO
=max, V
IN
=0
@V
DD_IO
=max, V
IN
=0
@V
DD_IO
=max, V
IN
=0V
@f
IN
=1MHz,T
CASE
=25C, V
IN
=2.5V
Min
2.18
Max
Unit
V
V
μA
μA
mA
μA
mA
mA
μA
mA
μA
mA
mA
mA
pF
High-Level Output Voltage
1
Low-Level Output Voltage
1
High-Level Input Current
High-Level Input Current
High-Level Input Current
Low-Level Input Current
Low-Level Input Current
Low-Level Input Current
Three-State Leakage Current High
Three-State Leakage Current High
Three-State Leakage Current Low
Three-State Leakage Current Low
Three-State Leakage Current Low
Three-State Leakage Current Low
Input Capacitance
2,3
1
Applies to output and bidirectional pins.
2
Applies to all signals.
3
Guaranteed but not tested.
0.4
10
50
0.76
10
0.76
0.1
10
0.76
10
0.76
0.1
7.6
3
0.3
0.3
0.03
0.3
0.3
0.03
4
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