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參數資料
| 型號： | ADSP-TS203S |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | TigerSHARC Embedded Processor |
| 中文描述： | TigerSHARC系列嵌入式處理器 |
| 文件頁數： | 13/40頁 |
| 文件大?。?/td> | 609K |
| 代理商： | ADSP-TS203S |
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ADSP-TS203S
Preliminary Technical Data
Rev. PrB
|
Page 13 of 40
|
December 2003
Table 5. Pin Definitions—External Port Bus Controls
Signal
ADDR31–0
Type
I/O/T
(pu_ad)
Term
nc
Description
Address Bus. The DSP issues addresses for accessing memory and peripherals on
these pins. In a multiprocessor system, the bus master drives addresses for accessing
internal memory or I/O processor registers of other ADSP-TS203S processors. The DSP
inputs addresses when a host or another DSP accesses its internal memory or I/O
processor registers.
External Data Bus. The DSP drives and receives data and instructions on these pins.
Pullup/down resistors on unused DATA pins are unnecessary.
Memory Read. RD is asserted whenever the DSP reads from any slave in the system,
excluding SDRAM. When the DSP is a slave, RD is an input and indicates read trans-
actions that access its internal memory or universal registers. In a multiprocessor
system, the bus master drives RD. RD changes concurrently with ADDR pins.
Write Low. WRL is asserted when the ADSP-TS203S processor writes to the external
bus (host, memory or DSP). An external master (host or DSP) asserts WRL for writing
to a DSP’s internal memory. In a multiprocessor system, the bus master drives WRL.
WRL changes concurrently with ADDR pins. When the DSP is a slave, WRL is an input
and indicates write transactions that access its internal memory or universal registers.
Acknowledge. External slave devices can de-assert ACK to add wait states to external
memory accesses. ACK is used by I/O devices, memory controllers and other periph-
erals on the data phase. The DSP can de-assert ACK to add wait states to read and
write accesses of its internal memory. The pullup is 50
on low-to-high transactions
and is 500
on all other transactions.
Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During
reset, the DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a multipro-
cessor system, the DSP bus master drives BMS. For details, see
Reset and Booting on
page 9
and see the EBOOT signal description in
Table 15 on page 19
.
Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0
or 1 respectively. MS1–0 are decoded memory address pins that change concurrently
with ADDR pins. When ADDR31:27 = 0b00110, MS0 is asserted. When ADDR31:27 =
0b00111, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1–0.
Memory Select Host. MSH is asserted whenever the DSP accesses the host address
space (ADDR31 = 0b1). MSH is a decoded memory address pin that changes concur-
rently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH.
Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading
or writing data associated with consecutive addresses. A slave device can ignore
addresses after the first one and increment an internal address counter after each
transfer. For host-to-DSP burst accesses, the DSP increments the address automati-
cally while BRST is asserted.
Test Mode 4. Must be pulled up to V
DD_IO
with a 5 k
resistor.
DATA31–0
I/O/T
(pu_ad)
I/O/T
(pu_0)
nc
RD
epu
WRL
I/O/T
(pu_0)
epu
ACK
I/O/T/OD
(pu_od_0)
epu
BMS
O/T
(pu_0)
au
MS1–0
O/T
(pu_0)
nc
MSH
O/T
(pu_0)
nc
BRST
I/O/T
(pu_0)
nc
TM4
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
I/O/T
epu
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相關代理商/技術參數 |
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|---|---|
| ADSP-TS203SABP-050 | 功能描述:IC DSP FLOAT/FIXED 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS203SABP-05X | 制造商:Analog Devices 功能描述: |
| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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