參數(shù)資料
型號： ADSP-TS203S
廠商： Analog Devices, Inc.
英文描述： TigerSHARC Embedded Processor
中文描述： TigerSHARC系列嵌入式處理器
文件頁數(shù)： 15/40頁
文件大?。?/td> 609K
代理商： ADSP-TS203S
ADSP-TS203S
Preliminary Technical Data
Rev. PrB
|
Page 15 of 40
|
December 2003
Table 7. Pin Definitions—External Port DMA/Flyby
Signal
DMAR3–0
Type
I/A
Term
epu
Description
DMA Request Pins. Enable external I/O devices to request DMA services from the DSP.
In response to DMARx, the DSP performs DMA transfers according to the DMA
channel’s initialization. The DSP ignores DMA requests from uninitialized channels.
I/O Write. When a DSP DMA channel initiates a flyby mode read transaction, the DSP
asserts the IOWR signal during the data cycles. This assertion makes the I/O device
sample the data instead of the TigerSHARC.
I/O Read. When a DSP DMA channel initiates a flyby mode write transaction, the DSP
asserts the IORD signal during the data cycle. This assertion with the IOEN makes the
I/O device drive the data instead of the TigerSHARC.
I/O Device Output Enable. Enables the output buffers of an external I/O device for fly-
by transactions between the device and external memory. Active on fly-by
transactions.
IOWR
O/T
(pu_0)
nc
IORD
O/T
(pu_0)
nc
IOEN
O/T
(pu_0)
nc
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
MSSD3–0
Type
I/O/T
(pu_0)
Term
nc
Description
Memory Select SDRAM. MSSD0, MSSD1, MSSD2, or MSSD3 is asserted whenever the
DSP accesses SDRAM memory space. MSSD3–0 are decoded memory address pins
that are asserted whenever the DSP issues an SDRAM command cycle (access to
ADDR31:30 = 0b01—except reserved spaces shown in
Figure 3 on page 6
). In a multi-
processor system, the master DSP drives MSSD3–0.
Row Address Select. When sampled low, RAS indicates that a row address is valid in
a read or write of SDRAM. In other SDRAM accesses, it defines the type of operation
to execute according to SDRAM specification.
Column Address Select. When sampled low, CAS indicates that a column address is
valid in a read or write of SDRAM. In other SDRAM accesses, it defines the type of
operation to execute according to the SDRAM specification.
Low Word SDRAM Data Mask. When sampled high, three-states the SDRAM DQ
buffers. LDQM is valid on SDRAM transactions when CAS is asserted, and inactive on
read transactions.
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation
while the DSP executes non-SDRAM transactions.
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend
modes. A slave DSP in a multiprocessor system does not have the pullup or pulldown.
A master DSP (or ID=0 in a single processor system) has a pullup before granting the
bus to the host, except when the SDRAM is put in self refresh mode. In self refresh
mode, the master has a pulldown before granting the bus to the host.
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an
SDRAM write access. When sampled high while CAS is active, SDWE indicates an
SDRAM read access. In other SDRAM accesses, SDWE defines the type of operation to
execute according to SDRAM specification.
RAS
I/O/T
(pu_0)
nc
CAS
I/O/T
(pu_0)
nc
LDQM
O/T
(pu_0)
nc
SDA10
O/T
(pu_0)
I/O/T
(pu_m/
pd_m)
nc
SDCKE
nc
SDWE
I/O/T
(pu_0)
nc
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
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