- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19463 > ADSP-TS101SAB1Z100 (Analog Devices Inc)IC DSP CTRLR 128BIT BUS 625-BGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ADSP-TS101SAB1Z100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CTRLR 128BIT BUS 625-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TigerSHARC® |
| 類型： | 定點(diǎn)/浮點(diǎn) |
| 接口： | 主機(jī)接口，連接端口，多處理器 |
| 時(shí)鐘速率： | 300MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 768kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 625-BBGA |
| 供應(yīng)商設(shè)備封裝： | 625-PBGA（27x27） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Rev. C
|
Page 16 of 48
|
May 2009
ADSP-TS101S
Table 8. Pin Definitions—External Port SDRAM Controller
Signal
Type
Term
Description
MSSD
1
I/O/T (pu
2)
nc
Memory Select SDRAM. MSSD is asserted whenever the DSP accesses SDRAM memory space.
MSSD is a decoded memory address pin that is asserted whenever the DSP issues an SDRAM
command cycle (access to ADDR31:26 = 0b000001). MSSD in a multiprocessor system is driven
by the master DSP.
RAS
I/O/T (pu
2)
nc
Row Address Select. When sampled low, RAS indicates that a row address is valid in a read or
write of SDRAM. In other SDRAM accesses, RAS defines the type of operation to execute
according to SDRAM specification.
CAS1
I/O/T (pu2)
nc
Column Address Select. When sampled low, CAS indicates that a column address is valid in a
read or write of SDRAM. In other SDRAM accesses, CAS defines the type of operation to execute
according to the SDRAM specification.
LDQM
O/T (pu
2)
nc
Low Word SDRAM Data Mask. When LDQM is sampled high, the DSP three-states the SDRAM
DQ buffers. LDQM is valid on SDRAM transactions when CAS is asserted and is inactive on read
transactions. On write transactions, LDQM is active when accessing an odd address word on a
64-bit memory bus to disable the write of the low word.
HDQM
O/T (pu
2)
nc
High Word SDRAM Data Mask. When HDQM is sampled high, the DSP three-states the SDRAM
DQ buffers. HDQM is valid on SDRAM transactions when CAS is asserted and is inactive on read
transactions. On write transactions, HDQM is active when accessing an even address in word
accesses or is active when memory is configured for a 32-bit bus to disable the write of the high
word.
SDA10
O/T (pu
2)
nc
SDRAM Address bit 10 pin. Separate A10 signals enable SDRAM refresh operation while the DSP
executes non-SDRAM transactions.
SDCKE
1, 3
I/O/T
(pu/pd2)
nc
SDRAM Clock Enable. Activates the SDRAM clock for SDRAM self-refresh or suspend modes. A
slave DSP in a multiprocessor system does not have the pull-up or pull-down. A master DSP (or
ID = 0 in a single processor system) has a 100 k
pull-up before granting the bus to the host,
except when the SDRAM is put in self-refresh mode. In self-refresh mode, the master has a
100 k
pull-down before granting the bus to the host.
SDWE1
I/O/T (pu2)
nc
SDRAM Write Enable. When sampled low while CAS is active, SDWE indicates an SDRAM write
access. When sampled high while CAS is active, SDWE indicates an SDRAM read access. In other
SDRAM accesses, SDWE defines the type of operation to execute according to SDRAM
specification.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
2 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances.
3 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
Table 9. Pin Definitions—JTAG Port
Signal
Type
Term
Description
EMU
O (o/d)
nc
1
Emulation. Connected only to the DSP’s JTAG emulator target board connector.
TCK
I
epd or
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
TDI
2
I (pu
3)nc1
Test Data Input (JTAG). A serial data input of the scan path.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBM08DSEF | CONN EDGECARD 16POS .156 EYELET |
| EBM08DSAI | CONN EDGECARD 16POS R/A .156 SLD |
| VE-2WP-CY-F4 | CONVERTER MOD DC/DC 13.8V 50W |
| 171-009-213R031 | CONN DB9 FEMALE DIP SLD NICKEL |
| TPSC106K020H0700 | CAP TANT 10UF 20V 10% 2312 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-TS101SAB2-000 | 功能描述:IC DSP CONTROLLER 6MBIT 484 BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS101SAB2-050 | 制造商:Analog Devices 功能描述:TIGERSHARC - Trays |
| ADSP-TS101SAB2-100 | 功能描述:IC DSP CONTROLLER 6MBIT 484 BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS101SAB2Z000 | 功能描述:IC DSP FLOAT/FIXED 250MHZ 484BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS101SAB2Z100 | 功能描述:IC DSP CTRLR 6MBIT 300MHZ 484BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。