參數(shù)資料
型號： ADSP-TS101SAB1Z100
廠商： Analog Devices Inc
文件頁數(shù)： 11/48頁
文件大?。?/td> 0K
描述： IC DSP CTRLR 128BIT BUS 625-BGA
標(biāo)準(zhǔn)包裝： 1
系列： TigerSHARC®
類型： 定點/浮點
接口： 主機(jī)接口，連接端口，多處理器
時鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 768kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 625-BBGA
供應(yīng)商設(shè)備封裝： 625-PBGA（27x27）
包裝： 托盤
ADSP-TS101S
Rev. C
|
Page 19 of 48
|
May 2009
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an approximately 100 k pull-
down for the default value. If a strap pin is not connected to an
external pull-up or logic load, the DSP samples the default value
during reset. If strap pins are connected to logic inputs, a stron-
ger external pull-down may be required to ensure default value
depending on leakage and/or low level input current of the logic
load. To set a mode other than the default mode, connect the
strap pin to a sufficiently stronger external pull-up. In a multi-
processor system, up to eight DSPs may be connected on the
cluster bus, resulting in parallel combination of strap pin pull-
down resistors. Table 16 lists and describes each of the DSP’s
strap pins.
Table 15. Pin Definitions—Power, Ground, and Reference
Signal
Type
Term
Description
VDD
Pau
VDD pins for internal logic.
VDD_A
Pau
VDD pins for analog circuits. Pay critical attention to bypassing this supply.
VDD_IO
Pau
VDD pins for I/O buffers.
VREF
I
au
Reference voltage defines the trip point for all input buffers, except RESET, IRQ3–0, DMAR3–0,
ID2–0, CONTROLIMP2–0, TCK, TDI, TMS, and TRST. The value is 1.5 V ± 100 mV (which is the TTL
trip point). VREF can be connected to a power supply or set by a voltage divider circuit. The
voltage divider should have an HF decoupling capacitor (1 nF HF SMD) connected to VSS. Tie
the decoupling capacitor between VREF input and VSS, as close to the DSP’s pins as possible. For
VSS
Gau
Ground pins.
VSS_A
G
au
Ground pins for analog circuits.
NC
No connect. Do not connect these pins to anything (not to any supply, signal, or each other),
because they are reserved and must be left unconnected.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
Table 16. Pin Definitions—I/O Strap Pins
Signal
On Pin …
Description
EBOOT
BMS
EPROM boot.
0 = boot from EPROM immediately after reset (default)
1 = idle after reset and wait for an external device to boot DSP through the
external port or a link port
IRQEN
BM
Interrupt Enable.
0 = disable and set IRQ3–0 interrupts to level sensitive after reset (default)
1 = enable and set IRQ3–0 interrupts to edge sensitive immediately after reset
TM1
L2DIR
Test Mode 1.
0 = required setting during reset.
1 = reserved.
TM2
TMR0E
Test Mode 2.
0 = required setting during reset.
1 = reserved.
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