IDD-TYP " />
參數(shù)資料
型號: ADSP-BF544BBCZ-4A
廠商: Analog Devices Inc
文件頁數(shù): 32/100頁
文件大小: 0K
描述: IC CCD SIGNAL PROCESSOR 400BGA
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點
接口: CAN,SPI,SSP,TWI,UART
時鐘速率: 400MHz
非易失內(nèi)存: 外部
芯片上RAM: 196kB
電壓 - 輸入/輸出: 2.50V,3.30V
電壓 - 核心: 1.25V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 400-CSPBGA(17x17)
包裝: 托盤
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 37 of 100
|
February 2010
IDD-TYP
VDDINT Current
VDDINT = 1.10 V,
fCCLK = 300 MHz,
fSCLK = 25 MHz,
TJ = 25°C,
ASF = 1.00
145
178
mA
IDD-TYP
VDDINT Current
VDDINT = 1.20 V,
fCCLK = 400 MHz,
fSCLK = 25 MHz,
TJ = 25°C,
ASF = 1.00
199
239
mA
IDD-TYP
VDDINT Current
VDDINT = 1.25 V,
fCCLK = 533 MHz,
fSCLK = 25 MHz,
TJ = 25°C,
ASF = 1.00
301
mA
IDD-TYP
VDDINT Current
VDDINT = 1.35 V,
fCCLK = 600 MHz,
fSCLK = 25 MHz,
TJ = 25°C,
ASF = 1.00
360
mA
IDDHIBERNATE
13, 14 Hibernate State
Current
VDDEXT = VDDVR = VDDUSB
= 3.30 V,
VDDDDR = 2.5 V,
TJ = 25°C,
CLKIN= 0 MHz with
voltage regulator off
(VDDINT = 0 V)
60
A
IDDRTC
VDDRTC Current
VDDRTC = 3.3 V, TJ = 25°C
20
A
IDDUSB-FS
VDDUSB Current in
Full/Low Speed Mode
VDDUSB = 3.3 V,
TJ =25°C, Full Speed
USB Transmit
9
mA
IDDUSB-HS
VDDUSB Current in High
Speed Mode
VDDUSB = 3.3 V,
TJ =25°C, High Speed
USB Transmit
25
mA
IDDDEEPSLEEP
DDINT Current in Deep
Sleep Mode
fCCLK = 0 MHz,
fSCLK = 0 MHz
IDDSLEEP
VDDINIT Current in Sleep
Mode
fCCLK = 0 MHz,
fSCLK > 0 MHz
IDDDEEPSLEEP
+ (0.77
×
VDDINT ×
fSCLK)
IDDDEEPSLEEP
+ (0.77
×
VDDINT ×
fSCLK)
mA
16
IDDINT
VDDINT Current
fCCLK > 0 MHz,
fSCLK > 0 MHz
IDDSLEEP +
× ASF)
IDDSLEEP +
× ASF)
mA
1 Applies to all nonautomotive 400 MHz speed grade models. See Ordering Guide.
2 Applies to all 533 MHz and 600 MHz speed grade models and automotive 400 MHz speed grade models. See Ordering Guide.
3 Applies to output and bidirectional pins, except USB_VBUS and the pins listed in table note 4.
4 Applies to pins DA0–12, DBA0–1, DQ0–15, DQS0–1, DQM0–1, DCLK1–2, DCLK1–2, DCS0–1, DCLKE, DRAS, DCAS, and DWE.
5 Applies to all input pins except JTAG inputs.
6 Applies to JTAG input pins (TCK, TDI, TMS, TRST).
7 Applies to DDR_VREF pin.
8 Absolute value.
9 For DDR pins (DQ0-15, DQS0-1), test conditions are VDDDDR = Maximum, VIN = VDDDDR Maximum.
10Applies to three-statable pins.
11For DDR pins (DQ0-15, DQS0-1), test conditions are V
DDDDR = Maximum, VIN = 0V.
12Guaranteed, but not tested
Nonautomotive 400 MHz1
All Other Devices2
Parameter
Test Conditions
Min
Typ
Max
Min
Typ
Max
Unit
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