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| 型號： | ADSP-BF544BBCZ-4A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 400BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | CAN，SPI，SSP，TWI，UART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 196kB |
| 電壓 - 輸入/輸出： | 2.50V，3.30V |
| 電壓 - 核心： | 1.25V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 400-CSPBGA（17x17） |
| 包裝： | 托盤 |
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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 21 of 100
|
February 2010
sion 2.1. An I2C multiplexer can be used to select one
processor at a time when booting multiple processors from
a single TWI.
Boot from UART host (BMODE = 0x7)—In this mode, the
processor uses UART1 as the booting source. Using an
autobaud handshake sequence, a boot-stream-formatted
program is downloaded by the host. The host agent selects
a bit rate within the UART’s clocking capabilities.
When performing the autobaud, the UART expects an “@”
(0x40) character (eight data bits, one start bit, one stop bit,
no parity bit) on the UART1RX pin to determine the bit
rate. It then replies with an acknowledgement, which is
composed of four bytes (0xBF, the value of UART1_DLL,
the value of UART1_DLH, and finally 0x00). The host can
then download the boot stream. The processor deasserts
the UART1RTS output to hold off the host; UART1CTS
functionality is not enabled at boot time.
Boot from (DDR) SDRAM (BMODE = 0xA)—In this
mode, the boot kernel starts booting from address
0x0000 0010. This is a warm boot scenario only. The
SDRAM is expected to contain a valid boot stream and the
SDRAM controller must have been configured by the OTP
settings.
Boot from 8-bit and 16-bit external NAND flash memory
(BMODE = 0xD)—In this mode, auto detection of the
NAND flash device is performed. The processor configures
PORTJ GPIO pins PJ1 and PJ2 to enable the ND_CE and
ND_RB signals, respectively. For correct device operation,
pull-up resistors are required on both ND_CE (PJ1) and
ND_RB (PJ2) signals. By default, a value of 0x0033 is writ-
ten to the NFC_CTL register. The booting procedure
always starts by booting from byte 0 of block 0 of the
NAND flash device. In this boot mode, the HWAIT signal
does not toggle. The respective GPIO pin remains in the
high-impedance state.
NAND flash boot supports the following features:
Device auto detection
Error detection and correction for maximum
reliability
No boot stream size limitation
Peripheral DMA via channel 22, providing efficient
transfer of all data (excluding the ECC parity data)
Software-configurable boot mode for booting from
boot streams expanding multiple blocks, including
bad blocks
Software-configurable boot mode for booting from
multiple copies of the boot stream allowing for han-
dling of bad blocks and uncorrectable errors
Configurable timing via OTP memory
Small page NAND flash devices must have a 512-byte page
size, 32 pages per block, a 16-byte spare area size and a bus
configuration of eight bits. By default, all read requests
from the NAND flash are followed by four address cycles.
If the NAND flash device requires only three address
cycles, then the device must be capable of ignoring the
additional address cycle.
The small page NAND flash device must comply with the
following command set:
For large page NAND flash devices, the 4-byte electronic
signature is read in order to configure the kernel for boot-
ing. This allows support for multiple large page devices.
The fourth byte of the electronic signature must comply
with the specifications in Table 10.
Any configuration from Table 10 that also complies with
the command set listed below is directly supported by the
boot kernel. There are no restrictions on the page size or
block size as imposed by the small-page boot kernel.
Large page devices must support the following command set:
Large page devices must not support or react to NAND flash
command 0x50. This is a small page NAND flash command
used for device auto detection.
Reset: 0xFF
Read lower half of page: 0x00
Read upper half of page: 0x01
Read spare area: 0x50
Table 10. Byte 4 Electronic Signature Specification
Page Size
(excluding spare
area)
D1:D0
00
1K bytes
01
2K bytes
10
4K bytes
11
8K bytes
Spare Area Size
D2
0
8 bytes/512 bytes
1
16 bytes/512 bytes
Block Size
(excluding spare
area)
D5:4
00
64K bytes
01
128K bytes
10
256K bytes
11
512K bytes
Bus Width
D6
0
x8
1x16
Not Used for
Configuration
D3, D7
Reset: 0xFF
Read Electronic Signature: 0x90
Read: 0x00, 0x30 (confirm command)
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| ADSP-BF544BBCZ-5A | 功能描述:IC DSP 16BIT 533MHZ 400CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF544BBCZ-5X | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE CONVERGENT MULTIMEDIA BLACKFIN PROCESSOR - Trays |
| ADSP-BF544MBBCZ-5M | 功能描述:IC DSP 16BIT 533MHZ MDDR 400CBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF547BBCZ-5A | 功能描述:IC DSP 16BIT 533MHZ 400CSBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF547BBCZ-5X | 制造商:Analog Devices 功能描述:- Trays |
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