參數(shù)資料
型號(hào)： ADSP-BF544BBCZ-4A
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 10/100頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 400BGA
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類(lèi)型： 定點(diǎn)
接口： CAN，SPI，SSP，TWI，UART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： 外部
芯片上RAM： 196kB
電壓 - 輸入/輸出： 2.50V，3.30V
電壓 - 核心： 1.25V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 400-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 400-CSPBGA（17x17）
包裝： 托盤(pán)
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 17 of 100
|
February 2010
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. In the sleep mode, assertion of a wakeup event
enabled in the SIC_IWRx register causes the processor to sense
the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
In the sleep mode, system DMA access to L1 memory is not
supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This
powered-down mode can only be exited by assertion of the reset
interrupt (RESET) or by an asynchronous interrupt generated
by the RTC. In deep sleep mode, an asynchronous RTC inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the full on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by using the
bfrom_SysControl() function in the on-chip ROM. This sets the
internal power supply voltage (VDDINT) to 0 V to provide the
greatest power savings mode. Any critical information stored
internally (memory contents, register contents, and so on) must
be written to a non-volatile storage device prior to removing
power if the processor state is to be preserved.
Since VDDEXT is still supplied in this mode, all of the external
pins three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to have power
still applied without drawing unwanted current.
The internal supply regulator can be woken up by CAN, by the
MXVR, by the keypad, by the up/down counter, by the USB,
and by some GPIO pins. It can also be woken up by a real-time
clock wakeup event or by asserting the RESET pin. Waking up
from hibernate state initiates the hardware reset sequence.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in hibernate
state. State variables may be held in external SRAM or DDR
memory.
Figure 5. MXVR MOST Connection
600Z
MLF_M
MOST
NETWORK
AUDIO
CHANNELS
GNDMP
VDDMP
MOST FOT
TXVCC
TX_DATA
RX_DATA
STATUS
AUDIO DAC
27
R1
330
C1
0.047 F
0.1 F
0.01 F
C2
330pF
ADSP-BF549
MXI
MXO
MLF_P
PG11/
MTXON
PH5/MTX
PH6/MRX
PH7/
MRXON
PC1/MMCLK
MFS
PC5/MBCLK
PC3/TSCLK0
PC7/RSCLK0
PC4/RFS0
PC2/DT0PRI
SDATA
L/RCLK
BCLK
MCLK
33
1.25V
GND
VDDINT
1%
2% PPS
0
TXGND
5.0V
RXVCC
RXGND
600Z
10k
24.576MHz
XN4114
Table 5. Power Settings
M
o
de/
State
PLL
By
p
a
ss
e
d
Co
re
Cl
o
ck
(CC
L
K
)
Sys
te
m
Cl
o
ck
(S
CLK)
Co
re
Po
w
e
r
Full On
Enabled
No
Enabled
On
Active
Enabled/
Disabled
Yes
Enabled
On
Sleep
Enabled
-
Disabled
Enabled
On
Deep Sleep
Disabled
-
Disabled
On
Hibernate
Disabled
-
Disabled
Off
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