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參數(shù)資料
| 型號(hào)： | ADSP-2141LKS-N1 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 加密電路 |
| 英文描述： | DSP |
| 中文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP208 |
| 封裝： | METRIC, PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 9/39頁(yè) |
| 文件大小： | 257K |
| 代理商： | ADSP-2141LKS-N1 |
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REV. 0
ADSP-2141L
–9–
PIN FUNCTIONS
I/O Descriptions
This section describes the physical I/O hardware on the ADSP-2141L.
PIN FUNCTION DESCRIPTIONS–I/O Hardware
# of
Pins
Input/
Output
Pin Name
Function
External Memory Bus
Address [25:0]
26
O
Address Output Pins for Program, Data, Byte and I/O Spaces (13 Bits 2183, 13Bits
from Overlay Register) Note: A0 not used for 32-bit memory.
Data I/O Pins for Program and Data Memory Spaces
D31:0 are used for wide-bus data memory.
D23:0 are used for DSP Program RAM.
D23:8 are used for I/O Space.
D23:8 are used for DSP Data RAM.
D15:8 are used for byte memory.
D23:16 are also used as Byte Space Addresses
Data [31:0]
32
I/O
Interrupts
IRQ2
IRQL0
IRQL1
IRQE
1
1
1
1
I
I
I
I
Edge- or Level-Sensitive Interrupt Request
Level-Sensitive Interrupt Requests
Level-Sensitive Interrupt Requests
Edge-Sensitive Interrupt Request
Bus Signals
BR
BG
BGH
PMS
DMSL
DMSH
BMS
IOMS
CMS
RD
WR
1
1
1
1
1
1
1
1
1
1
1
I
O
O
O
O
O
O
O
O
O
O
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Program Memory Select Output
Data Memory Select Output (Lower 16 Bits for 32-Bit DM)
Upper Memory Select Output (Upper 16 Bits for 32-Bit DM, Not Used for 16-Bit DM)
Byte Memory Select Output
I/O Space Memory Select Output
Combined Memory Select Output (
PMS
,
DMS
*,
IOMS
,
BMS
)
Memory Read Enable Output
Memory Write Enable Output
Miscellaneous
MMAP
BMODE
CLKIN, XTAL
CLKOUT
1
1
2
1
I
I
I
O
Memory Map Select Input (1 = Overlay External at 0x0000)
Boot Option Control Input (0 = BDMA, 1 = IDMA)
Clock or Quartz Crystal Input (1/2 of the ADSP-2141 Clock)
Processor Clock Output
Serial Ports
SPORT0
SCLK0
DR0
RFS0
DT0
TFS0
SPORT1
Port Configuration
(System Control Reg)
–>
SCLK1
DR1
RFS1
DT1
TFS1
1
1
1
1
1
I/O
I
I/O
O
I/O
Serial Port 0 Clock
Serial Port 0 Receive Data Input
Serial Port 0 Receive Frame Sync
Serial Port 0 Transmit Data Output
Serial Port 0 Transmit Frame Sync
1 = Serial Port
Serial Port 1
Serial Port 1 Receive Data Input
Serial Port 1 Receive Frame Sync
Serial Port 1 Transmit Data Output
Serial Port 1 Transmit Frame Sync
0 = Other
Clock
Flag In
IRQ0
Flag Out
IRQ1
1
1
1
1
1
I/O
I
I/O
O
I/O
Power-Down
PWD
PWDACK
1
1
I
O
Power-Down Initiate Control
Power-Down Acknowledge
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADSP-2141LKSZ-N1 | 制造商:Analog Devices 功能描述: |
| ADSP2142MKS300X | 制造商:AD 功能描述:* |
| ADSP-21462W | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor material that is subject to change without notice |
| ADSP-21465W | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor material that is subject to change without notice |
| ADSP-21467 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor material that is subject to change without notice |
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