參數(shù)資料
型號(hào)： ADSP-2141LKS-N1
廠商： ANALOG DEVICES INC
元件分類： 加密電路
英文描述： DSP
中文描述： TELECOM, DATA ENCRYPTION CIRCUIT, PQFP208
封裝： METRIC, PLASTIC, QFP-208
文件頁(yè)數(shù)： 11/39頁(yè)
文件大?。?/td> 257K
代理商： ADSP-2141LKS-N1
REV. 0
ADSP-2141L
–11–
IDMA Mode Multiplex Bus Pin Definition
IDMA Port (218x Mode)
PIN FUNCTION DESCRIPTIONS—IDMA Mode Multiplex Bus
Pin Name
IDMA Name
Pins
I/O
Description
MPLX5
MPLX6
MPLX7
MPLX8
MPLX9
MPLX10
MPLX11
MPLX12
MPLX_BUS
IRD
IWR
IS
IAL
IACK
FL0
FL1
FL2
IAD
1
1
1
1
1
1
1
1
16
I
I
I
I
O
O
O
O
I/O
IDMA Port Read Input
IDMA Port Write Input
IDMA Port Select
IDMA Port Address Latch
IDMA Port Access Ready Acknowledge
Output Flags
Output Flags
Output Flags
IDMA Data I/O
PCI Port
PIN FUNCTION DESCRIPTIONS—PCI Mode Multiplex Bus
Pin Name
PCI Name
Pins
I/O
Description
MPLX1
MPLX2
MPLX3
MPLX4
MPLX5
MPLX6
MPLX7
MPLX8
MPLX9
MPLX10
MPLX11
MPLX12
MPLX_BUS
Pci_
cbe3
Pci_
cbe2
Pci_
cbe1
Pci_
cbe0
Pci_idsel
Pci_
gnt
Pci_
frame
Pci_
devsel
Pci_
trdy
Pci_
perr
Pci_
serr
Pci_
req
Pci_ad15:0
Pci_ad31:16
Pci_
intA
1
1
1
1
1
1
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I/O
I/O
I/O
O
Bus Command / Byte Enable 3
Bus Command / Byte Enable 2
Bus Command / Byte Enable 1
Bus Command / Byte Enable 0
Initialization Device Select
Bus Grant
Cycle Frame
Device Select
Target Ready
Parity Error
System Error
PCI Bus Request
32
1
I/O
O
PCI Address/Data Bus
PCI Interrupt A Request
PF7/
INT_H
SYSTEM INTERFACE
The ADSP-2141L may be integrated into a wide variety of sys-
tems, including those that already have a microprocessor and
those that will use the ADSP-2141L as the main processor. The
device can be configured into one of two Host Bus modes:
IDMA or PCI.
IDMA Bus Mode
The IDMA bus mode operates the same as in a native ADSP-
218x device, as described in this section.
The IDMA port provides an efficient means of communication
between a host system and the ADSP-2141L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers.
The IDMA port has a 16-bit multiplexed address and data bus,
and supports reading or writing 16-bit data (DM) or 24-bit
program memory (PM). The IDMA port is completely asyn-
chronous and can be written to while the ADSP-2141L is oper-
ating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
The IDMA port access occurs in two phases. The first is the
IDMA address latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value to the IDMAA register.
Once the address is stored, data can either be read from or
written to the ADSP-2141L’s on-chip memory. Asserting the
select line (
IS
) and the appropriate read or write line (
IRD
and
IWR
respectively) signals the ADSP-2141L that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
an additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the ADSP-2141L can also
specify the starting address and data format for DMA operation.
Figure 6 illustrates a typical system configuration for the
IDMA mode.
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