參數(shù)資料
型號: ADSP-21366SCSQ-ENG
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SHARC Processor
中文描述: 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝: MS-026BFB-HD, HSLQFP-144
文件頁數(shù): 37/54頁
文件大?。?/td> 559K
代理商: ADSP-21366SCSQ-ENG
ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 37 of 54
|
September 2004
SPDIF Transmitter Input Data Timing
The timing requirements for the Input port are given in
Table 32
. Input Signals (SCLK, FS, SDATA) are routed to the
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Over Sampling Clock (TXCLK) Switching Characteristics
SPDIF Transmitter has an over sampling clock. This TXCLK
input is divided down to generate the Biphase Clock.
Table 32. SPDIF Transmitter Input Data Timing
Parameter
Timing Requirements
t
SIFS
1
t
SIHFS
1
t
SISD
1
t
SIHD
1
t
SISCLKW
t
SISCLK
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
Min
Max
Unit
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
4
5.5
4
5.5
9
20
ns
ns
ns
ns
ns
ns
Figure 30. SPDIF Transmitter Input Timing
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
SAMPLE EDGE
t
SISD
t
SIHD
t
SISFS
t
SIHFS
t
SISCLKW
DAI_P20-1
(SDATA)
Table 33. Over Sampling Clock (TXCLK) Switching Characteristics
Parameter
TXCLK Frequency for TXCLK = 768 × FS
TXCLK Frequency for TXCLK = 512 × FS
TXCLK Frequency for TXCLK = 384 × FS
TXCLK Frequency for TXCLK = 256 × FS
Frame Rate
Min
Max
147.5
98.4
73.8
49.2
192.0
Unit
MHz
MHz
MHz
MHz
MHz
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