- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374033 > ADSP-21366SCSQ-ENG (ANALOG DEVICES INC) SHARC Processor PDF資料下載
參數(shù)資料
| 型號： | ADSP-21366SCSQ-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PQFP144 |
| 封裝： | MS-026BFB-HD, HSLQFP-144 |
| 文件頁數(shù)： | 33/54頁 |
| 文件大?。?/td> | 559K |
| 代理商： | ADSP-21366SCSQ-ENG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 33 of 54
|
September 2004
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 29
. PDAP is the parallel mode operation of channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the
ADSP-2136x SHARC Processor Hardware Refer-
ence
. Note that the most significant 16 bits of external PDAP
data can be provided through either the parallel port AD15–0 or
the DAI_P20–5 pins. The remaining 4 bits can only be sourced
through DAI_P4–1. The timing below is valid at the
DAI_P20–1 pins or at the AD15–0 pins.
Table 29. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
t
SPCLKEN
1
t
HPCLKEN
1
t
PDSD
1
t
PDHD
1
t
PDCLKW
t
PDCLK
Min
Max
Unit
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
Clock Width
Clock Period
2.5
2.5
2.5
2.5
7
24
ns
ns
ns
ns
ns
ns
Switching Characteristics
t
PDHLDD
t
PDSTRB
1
Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
2 × t
CCLK
1 × t
CCLK
– 1
ns
ns
Figure 24. PDAP Timing
DAI_P20-1
(PDAP_CLK)
SAMPLE EDGE
t
PDSD
t
PDHD
t
SPCLKEN
t
HPCLKEN
t
PDCLKW
DATA
DAI_P20-1
(PDAP_CLKEN)
t
PDSTRB
t
PDHLDD
DAI_P20-1
(PDAP_STROBE)
t
PDCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21366 | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| ADSP-21366SKBC-ENG | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| ADSP-21365 | SHARC Processor |
| ADSP-21365SBBC-ENG | SHARC Processor |
| ADSP-21365SBBCZENG | SHARC Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21366SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKBC-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。