參數(shù)資料
型號(hào)： ADSP-21366SCSQ-ENG
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝： MS-026BFB-HD, HSLQFP-144
文件頁(yè)數(shù)： 35/54頁(yè)
文件大小： 559K
代理商： ADSP-21366SCSQ-ENG
ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 35 of 54
|
September 2004
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the drive
edge.
Table 31. SRC, Serial Output Port
Parameter
Timing Requirements
t
SIFS
1
t
SIHFS
1
t
SRCTDD
1
t
SRCTDH
1
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
Min
Max
Unit
FS Setup Before SCLK Rising Edge
FS Hold Before SCLK Rising Edge
Transmit Data Delay After SCLK Falling Edge
Transmit Data Hold After SCLK Falling Edge
4
5.5
ns
ns
ns
ns
7
2
Figure 26. SRC Serial Output Port Timing
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
SAMPLE EDGE
t
SIFS
t
SIHFS
t
SISCLKW
DAI_P20-1
(SDATA)
t
SRCTDD
t
SRCTDH
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