- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374033 > ADSP-21366SCSQ-ENG (ANALOG DEVICES INC) SHARC Processor PDF資料下載
參數(shù)資料
| 型號： | ADSP-21366SCSQ-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PQFP144 |
| 封裝： | MS-026BFB-HD, HSLQFP-144 |
| 文件頁數(shù)： | 27/54頁 |
| 文件大?。?/td> | 559K |
| 代理商： | ADSP-21366SCSQ-ENG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 27 of 54
|
September 2004
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21365/6 is accessing external memory space.
Table 22. 8-bit Memory Write Cycle
Parameter
Switching Characteristics:
t
ALEW
t
ADAS
1
t
ALERW
t
RWALE
t
WRH
t
ADAH
1
t
WW
t
ADWL
t
ADWH
t
DWS
t
DWH
t
DAWH
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t
PCLK
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7 x t
PCLK
(if FLASH_MODE is set else F = 0)
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
Min
Max
Unit
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
ALE Deasserted to Read/Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to next WR Falling Edge
Address/Data 15–0 Hold After ALE Deasserted
WR Pulse Width
Address/Data 15–8 to WR Low
Address/Data 15–8 Hold After WR High
Address/Data 7–0 Setup Before WR High
Address/Data 7–0 Hold After WR High
Address/Data to WR High
2 × t
PCLK
– 2
t
PCLK
– 2.5
2 × t
PCLK
– 2
H + 0.5
F + H + t
PCLK
– 2
t
PCLK
– 0.5
D – F – 2
t
PCLK
– 1.5
H
D – F + t
PCLK
– 4
H
D – F + t
PCLK
– 4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 19. Write Cycle For 8-Bit Memory Timing
AD15-8
VALID
ADDRESS
VALID ADDRESS
t
ADAS
AD7-0
ALE
RD
WR
t
ADAH
t
ADWH
t
ADWL
VALID DATA
t
DAWH
t
WRH
t
RWALE
VALID
ADDRESS
VALID DATA
t
ALEW
t
ALERW
t
WW
t
DWS
t
DWH
VALID ADDRESS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21366 | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| ADSP-21366SKBC-ENG | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| ADSP-21365 | SHARC Processor |
| ADSP-21365SBBC-ENG | SHARC Processor |
| ADSP-21365SBBCZENG | SHARC Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21366SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKBC-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。