參數(shù)資料
型號(hào)： ADSP-21366SBSQZENG
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝： LEAD FREE, MS-026BFB-HD, HSLQFP-144
文件頁(yè)數(shù)： 26/54頁(yè)
文件大?。?/td> 559K
代理商： ADSP-21366SBSQZENG
Rev. PrA
|
Page 26 of 54
|
September 2004
ADSP-21365/6
Preliminary Technical Data
Table 21. 16-bit Memory Read Cycle
Parameter
Timing Requirements
t
DRS
t
DRH
Min
Max
Unit
Address/Data 15–0 Setup Before RD High
Address/Data 15–0 Hold After RD High
3.3
0
ns
ns
Switching Characteristics
t
ALEW
t
ADAS
1
t
ALERW
t
RRH
t
RWALE
t
RDDRV
t
ADAH
1
t
ALEHZ
1
t
RW
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t
PCLK
H = t
PCLK
(if a hold cycle is specified, else H = 0)
F = 7 x t
PCLK
(if FLASH_MODE is set else F = 0)
1
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
ALE Deasserted to Read Asserted
Delay Between RD Rising Edge to Next Falling Edge.
Read Deasserted to ALE Asserted
RD Address Drive After Read High
Address/Data 15–0 Hold After ALE Deasserted
ALE Deasserted to Address/Data15–0 in High Z
RD Pulse Width
2 × t
PCLK
– 2
t
PCLK
– 2.5
2 × t
PCLK
– 2
H + t
PCLK
– 1
F + H + 0.5
F + H + t
PCLK
– 1
t
PCLK
– 0.8
t
PCLK
– 0.8
D – 2
Figure 18. Read Cycle For 16-Bit Memory Timing
AD15-0
WR
t
DRS
t
DRH
t
RDDRV
t
ALEHZ
t
ADAH
t
ADAS
VALID ADDRESS
VALID DATA
VALID
ADDRESS
t
ALEW
t
RW
t
ALERW
t
RWALE
t
RRH
ALE
RD
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