參數(shù)資料
型號(hào): ADSP-21362BBCZ-1AA
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: SHARC Processor
中文描述: 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝: ROHS COMPLIANT, MO-205AE, CSBGA-136
文件頁(yè)數(shù): 36/52頁(yè)
文件大?。?/td> 1320K
代理商: ADSP-21362BBCZ-1AA
Rev. A
|
Page 36 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Pulse-Width Modulation Generators
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in
Table 33
are valid at the DAI_P20–1 pins.
This feature is not available on the ADSP-21363 models.
Table 32. PWM Timing
Parameter
Switching Characteristics
t
PWMW
t
PWMP
Min
Max
Unit
PWM Output Pulse Width
PWM Output Period
t
PCLK
– 2
2 × t
PCLK
– 1.5
(2
16
– 2) × t
PCLK
– 2
(2
16
– 1) × t
PCLK
ns
ns
Figure 26. PWM Timing
PWM
OUTPUTS
t
PWMW
t
PWMP
Table 33. SRC, Serial Input Port
Parameter
Timing Requirements
t
SRCSFS
1
t
SRCHFS
1
t
SRCSD
1
t
SRCHD
1
t
SRCCLKW
t
SRCCLK
Min
Max
Unit
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SDATA Setup Before SCLK Rising Edge
SDATA Hold After SCLK Rising Edge
Clock Width
Clock Period
3
3
3
3
36
80
ns
ns
ns
ns
ns
ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
Figure 27. SRC Serial Input Port Timing
DAI_P20
-
1
(SCLK)
DAI_P20
-
1
(FS)
SAMPLEEDGE
t
SRCCLK
t
SRCSFS
t
SRCHFS
DAI_P20
-
1
(SDATA)
t
SRCCLKW
t
SRCSD
t
SRCHD
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