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參數(shù)資料
| 型號(hào)： | ADSP-21161NKCA-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 50/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 225MBGA |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | 主機(jī)接口，連接端口，串行端口 |
| 時(shí)鐘速率： | 100MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 225-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 225-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 其它名稱： | ADSP-21161NKCA100 |
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Rev. C
|
Page 54 of 60
|
January 2013
OUTPUT DRIVE CURRENTS
Figure 34 shows typical I-V characteristics for the output driv-
ers of the ADSP-21161N. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The DSP is tested for output enable, disable, and hold time.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output has reached a specified high
or low trip point, as shown in the Output Enable/Disable dia-
gram (Figure 35). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to start
driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high-impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by V is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by the
following equation:
tDECAY = (CLV)/IL
The output disable time tDIS is the difference between tMEASURED
val from when the reference signal switches to when the output
voltage decays V from the measured output high or output low
voltage. tDECAY is calculated with test loads CL and IL, and with
V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the ADSP-21161N’s output voltage
and the input threshold for the device requiring the hold time. A
typical V will be 0.4 V. CL is the total bus capacitance (per data
line), and IL is the total leakage or three-state current (per data
line). The hold time will be tDECAY plus the minimum disable
time (i.e., tDATRWH for the write cycle).
Figure 34. Typical Drive Currents
SWEEP (VDDEXT) VOLTAGE – V
60
–10
–40
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
50
0
–20
–30
30
10
40
20
–50
–60
L
O
A
D
(V
D
E
X
T
)
C
U
R
E
N
T
–
m
A
VDDEXT = 3.47V, –40°C
VDDEXT = 3.3V, +25°C
VDDEXT = 3.13V, +105°C
VDDEXT = 3.47V, –40°C
VDDEXT = 3.3V, +25°C
80
–80
Figure 35. Output Enable/Disable
Figure 36. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 37. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS DRIVING
VOH (MEASURED) – V
VOL (MEASURED) + V
tMEASURED
VOH
(MEASURED)
VOL
(MEASURED)
2.0V
1.0V
VOH
(MEASURED)
VOL
(MEASURED)
HIGH IMPEDANCE STATE.
TESTCONDITIONS CAUSETHIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
OUTPUT STOPS DRIVING
tENA
tDECAY
1.5V
30pF
TO
OUTPUT
PIN
50
INPUT
OR
OUTPUT
1.5V
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| ADSP-21161NKCA-100Z | 制造商:Analog Devices 功能描述: |
| ADSP-21161NKCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NYCAZ110 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21261 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Embedded Processor |
| ADSP-21261SKBC-150 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 150MHz 150MIPS 136-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:150 MHZ, 32BIT DSP PROCESSOR. - Bulk |
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