參數(shù)資料
型號： ADSP-21160NKB-95
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： DSP Microcomputer
中文描述： 64-BIT, 47.5 MHz, OTHER DSP, PBGA400
封裝： 27 X 27 MM, METRIC, PLASTIC, BGA-400
文件頁數(shù)： 47/53頁
文件大?。?/td> 1680K
代理商： ADSP-21160NKB-95
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
47
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
Example:
Estimate P
EXT
with the following assumptions:
A system with one bank of external data memory—asyn-
chronous RAM (64-bit)
Four 64K × 16 RAM chips are used, each with a load of
10 pF
External data memory writes occur every other cycle, a
rate of 1/(2 t
CK
), with 50% of the pins switching
The bus cycle time is 47.5 MHz (t
CK
= 21 ns).
The P
EXT
equation is calculated for each class of pins that
can drive:
A typical power consumption can now be calculated for
these conditions by adding a typical internal power
dissipation:
P
TOTAL
=
P
EXT
+
P
INT
+
P
PLL
Where:
P
EXT
is from
Table 30
P
INT
is I
DDINT
× 1.9 V, using the calculation I
DDINT
listed in
Power Dissipation on page 46
P
PLL
is AI
DD
× 1.9 V, using the value for AI
DD
listed in
ABSOLUTE MAXIMUM RATINGS on page 15
Note that the conditions causing a worst-case P
EXT
are
different from those causing a worst-case P
INT
. Maximum
P
INT
cannot occur while 100% of the output pins are
switching from all ones to all zeros. Note also that it is not
common for an application to have 100% or even 50% of
the outputs switching simultaneously.
Test Conditions
The test conditions for timing parameters appearing in
ADSP-21160N specifications on page 13
include output
disable time, output enable time, and capacitive loading.
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay
from their output high or low voltage. The time for the
voltage on the bus to decay by
V is dependent on the
capacitive load, C
L
and the load current, I
L
. This decay time
can be approximated by the following equation:
t
DECAY
= (
C
L
V
)/
I
L
The output disable time t
DIS
is the difference between
t
MEASURED
and t
DECAY
as shown in
Figure 32
. The time t
MEASURED
is the interval from when the reference signal switches to
when the output voltage decays
V from the measured
output high or output low voltage. t
DECAY
is calculated with
test loads
C
L
and
I
L
, and with
V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time t
ENA
is the interval from
when a reference signal reaches a high or low voltage level
to when the output has reached a specified high or low trip
point, as shown in the Output Enable/Disable diagram
(
Figure 32
). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to
start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular
system, first calculate t
DECAY
using the equation given above.
Choose V to be the difference between the
ADSP-21160N’s output voltage and the input threshold for
the device requiring the hold time. A typical V will be
0.4 V. C
L
is the total bus capacitance (per data line), and I
L
is the total leakage or three-state current (per data line). The
hold time will be t
DECAY
plus the minimum disable time (i.e.,
t
DATRWH
for the write cycle).
Table 30. External Power Calculations (3.3 V Device)
Pin Type
Address
MS0
WRx
Data
CLKOUT
# of Pins
15
1
2
64
1
% Switching
50
0
–
50
–
× C
× 44.7 pF
× 44.7 pF
× 44.7 pF
× 14.7 pF
× 4.7 pF
× f
× 24 MHz
× 24 MHz
× 24 MHz
× 24 MHz
× 48 MHz
× VDD
2
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
× 10.9 V
= P
EXT
= 0.088 W
= 0.000 W
= 0.023 W
= 0.123 W
= 0.003 W
P
EXT
= 0.237 W
Figure 32. Output Enable/Disable
REFERENCE
SIGNAL
DIS
OUTPUT STARTS
DRIVING
V
OH
(MEASURED) –
V
V
OL
(MEASURED) +
t
DECAY
V
t
MEASURED
V
OH
(MEASURED)
V
OL
(MEASURED)
2.0V
1.0V
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
ENA
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ADSP-21160N Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21160NKB-X 制造商:Analog Devices 功能描述:
ADSP-21160NKBZ-100 功能描述:IC DSP CONTROLLER 32BIT 400-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21161N 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21161NCCA-100 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21161NCCAZ100 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
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