參數(shù)資料
型號(hào)： ADSP-21160N
廠商： Analog Devices, Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
中文描述： 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù)
文件頁數(shù)： 1/53頁
文件大小： 1680K
代理商： ADSP-21160N
a
Preliminary Technical Data
DSP Microcomputer
ADSP-21160N
This information applies to a product under development. Its characteristics and speci-
fications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise agreed to in
writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
www.analog.com
Analog Devices,Inc., 2002
REV. PrB
PRELIMINARY TECHNICAL DATA
SUMMARY
High-Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Graphics, Imaging, and
Communication
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Backwards-Compatible—Assembly Source Level
Compatible with Code for ADSP-2106x DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Integrated Peripherals—Integrated I/O Processor,
4M Bits On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
KEY FEATURES
95 MHz (10.5 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
570 MFLOPS Peak and 380 MFLOPS Sustained
Performance (Based on FIR)
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping and Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
IEEE 1149.1 JTAG Standard Test Access Port and
On-Chip Emulation
400-Ball 27
27 mm Metric PBGA Package
FUNCTIONAL BLOCK DIAGRAM
MULT
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 X 40-BIT
MULT
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEX)
16 X 40-BIT
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
60
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS, AND
DATA BUFFERS
I/O PROCESSOR
DMA
CONTROLLER
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
ADDR
DATA
DATA
DATA
ADDR
ADDR
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
DUAL-PORTED SRAM
JTAG
TEST AND
EMULATION
6
HOST PORT
ADDR BUS
MUX
IOA
18
IOD
64
MULTIPROCESSOR
INTERFACE
EXTERNAL
PORT
DATA BUS
MUX
64
32
32
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DAG1
8X4X32
32
16/32/40/48/64
32/40/64
CORE PROCESSOR
PROGRAM
SEQUENCER
DAG2
8X4X32
B
B
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