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參數(shù)資料
| 型號： | ADSP-21160N |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁數(shù)： | 12/53頁 |
| 文件大?。?/td> | 1680K |
| 代理商： | ADSP-21160N |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
12
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
CLKIN
I
Local Clock In. CLKIN is the ADSP-21160N clock input. The ADSP-21160N external
port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the
CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,
changed, or operated below the specified frequency.
Core/CLKIN Ratio Control. ADSP-21160N core clock (instruction cycle) rate is equal
to n CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
For clock configuration definitions, see the
RESET
& CLKIN
section of the
System
Design
chapter of the
ADSP-21160 SHARC DSP Hardware Reference
manual.
CLKOUT is driven at the CLKIN frequency by the ADSP-21160N. This output can
be three-stated by setting the COD bit in the SYSCON register. A keeper latch on the
DSP’s CLKOUT pin maintains the output at the level it was last driven (only enabled
on the ADSP-21160N with ID2-0 = 00x).
Processor Reset. Resets the ADSP-21160N to a known state and begins execution at
the program memory location specified by the hardware reset vector address. The
RESET
input must be asserted (low) at power-up.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k
internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
20 k
internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine.
TRST
must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21160N.
TRST
has a
20 k
internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21160N emulator target board
connector only. EMU has a 50 k
internal pull-up resistor.
Core Instruction Fetch. Signal is active low when an external instruction fetch is
performed. Driven by bus master only. Three-state when host is bus master.
CIF
has a
20k
internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x.
Core Power Supply. Nominally 1.9 V dc and supplies the DSP’s core processor
(40 pins).
I/O Power Supply. Nominally 3.3 V dc (43 pins).
Analog Power Supply. Nominally 1.9 V dc and supplies the DSP’s internal PLL (clock
generator). This pin has the same specifications as V
DDINT
, except that added filtering
circuitry is required.
For more information, see Power Supplies on page 6.
Analog Power Supply Return.
Power Supply Return. (82 pins)
Do Not Connect. Reserved pins that must be left open and unconnected (9 pins).
CLK_CFG3–0
I
CLKOUT
O/T
RESET
I/A
TCK
TMS
I
I/S
TDI
I/S
TDO
TRST
O
I/A
EMU
O (O/D)
CIF
O/T
V
DDINT
P
V
DDEXT
AV
DD
P
P
AGND
GND
NC
G
G
Table 3. Boot Mode Selection
EBOOT
LBOOT
BMS
Booting Mode
1
0
0
0
0
1
0
0
1
0
1
1
Output
1 (Input)
1 (Input)
0 (Input)
0 (Input)
x (Input)
EPROM (Connect
BMS
to EPROM chip select.)
Host Processor
Link Port
No Booting. Processor executes from external memory.
Reserved
Reserved
Table 2. Pin Function Descriptions (Continued)
Pin
Type
Function
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