參數(shù)資料
型號: ADSP-21160NKB-95
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: 64-BIT, 47.5 MHz, OTHER DSP, PBGA400
封裝: 27 X 27 MM, METRIC, PLASTIC, BGA-400
文件頁數(shù): 46/53頁
文件大?。?/td> 1680K
代理商: ADSP-21160NKB-95
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
46
REV. PrB
For current information contact Analog Devices at 800/262-5643
ADSP-21160N
April 2002
PRELIMINARY TECHNICAL DATA
Output Drive Currents
Figure 31
shows typical I–V characteristics for the output
drivers of the ADSP-21160N. The curves represent the
current drive capability of the output drivers as a function
of output voltage.
Power Dissipation
Total power dissipation has two components, one due to
internal circuitry and one due to the switching of external
output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved. Using
the current specifications (I
DDINPEAK
, I
DDINHIGH
, I
DDINLOW
, I
DDIDLE
)
from
Electrical Characteristics on page 13
and the cur-
rent-versus-operation information in
Table 29
, engineers
can estimate the ADSP-21160N’s internal power supply
(V
DDINT
) input current for a specific application, according
to the following formula:
The external component of total power dissipation is caused
by the switching of output pins. Its magnitude depends on:
the number of output pins that switch during each
cycle (O)
the maximum frequency at which they can switch (f)
their load capacitance (C)
their voltage swing (VDD)
and is calculated by:
P
EXT
=
O
×
C
×
V
DD
2
×
f
The load capacitance should include the processor’s
package capacitance (C
IN
). The switching frequency
includes driving the load high and then back low. Address
and data pins can drive high and low at a maximum rate of
1/(2t
CK
). The write strobe can switch every cycle at a
frequency of 1/t
CK
. Select pins switch at 1/(2t
CK
), but selects
can switch on each cycle.
Figure 31. ADSP-21160N Typical Drive Currents
SOURCE(V
DDEXT
)VOLTAGE–V
–120
0
3.5
0.5
1
1.5
2
2.5
3
S
D
)
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
V
DDEXT
=3.47V,–40°C
V
DDEXT
=3.3V,25°C
V
DDEXT
=3.13V,100°C
V
DDEXT
=3.47V,–40°C
V
DDEXT
=3.3V,25°C
V
DDEXT
=3.13V,100°C
% Peak
I
DDINPEAK
I
DDINHIGH
I
DDINLOW
I
I
DDINT
×
×
×
% High
% Low
+ % Idle
×
Table 29. ADSP-21160N Operation Types vs. Input Current
Operation
Instruction Type
Instruction Fetch
Core Memory Access
2
Peak Activity
1
Multifunction
Cache
2 per t
CK
cycle
(DM 64 and PM 64)
1 per 2 t
CCLK
cycles
1 per external port cycle ( 64)
Worst case
High Activity
1
Multifunction
Internal Memory
1 per t
CK
cycle
(DM 64)
1 per 2 t
CCLK
cycles
1 per external port cycle ( 64)
Random
Low Activity
1
Single Function
Internal Memory
None
Internal Memory DMA
External Memory DMA
Data bit pattern for core
memory access and DMA
None
None
N/A
1
Peak Activity=I
DDINPEAK
, High Activity=I
DDINHIGH
, and Low Activity=I
DDINLOW
. The state of the PEYEN bit (SIMD versus SISD mode) does not influence
these calculations.
2
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
CK
and t
CCLK
), see the timing ratio definitions
on page 16
.
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