參數(shù)資料
型號： ADSP-21160NCBZ-100
廠商： Analog Devices Inc
文件頁數(shù)： 8/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 400-PBGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標準包裝： 1
系列： SHARC®
類型： 浮點
接口： 主機接口，連接端口，串行端口
時鐘速率： 100MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.90V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤
ADSP-21160N
–16–
REV. 0
TIMING SPECIFICATIONS
The ADSP-21160N’s internal clock switches at higher frequen-
cies than the system input clock (CLKIN). To generate the
internal clock, the DSP uses an internal phase-locked loop
(PLL). This PLL-based clocking minimizes the skew between
the system clock (CLKIN) signal and the DSP’s internal clock
(the clock source for the external port logic and I/O pads).
The ADSP-21160N’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory, processor
core, link ports, serial ports, and external port (as required for
read/write strobes in asynchronous access mode). During reset,
program the ratio between the DSP’s internal clock frequency
and external (CLKIN) clock frequency with the CLK_CFG3–0
pins. Even though the internal clock is the clock source for the
external port, the external port clock always switches at the
CLKIN frequency. To determine switching frequencies for the
serial and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx for
the serial ports and LxCLKD1–0 for the link ports).
Note the following definitions of various clock periods that are a
function of CLKIN and the appropriate ratio control:
t
CCLK = (tCK) / CR
t
LCLK = (tCCLK)
LR
t
SCLK = (tCCLK)
SR
where:
LCLK = Link Port Clock
SCLK = Serial Port Clock
t
CK = CLKIN Clock Period
t
CCLK = (Processor) Core Clock Period
t
LCLK = Link Port Clock Period
t
SCLK = Serial Port Clock Period
CR = Core/CLKIN Ratio (2, 3, or 4:1,
determined by CLK_CFG3–0 at reset)
LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
determined by LxCLKD)
SR = Serial Port/Core Clock Ratio (wide range,
determined by
CLKDIV)
Use the exact timing information given. Do not attempt to derive
parameters from the addition or subtraction of others. While
addition or subtraction would yield meaningful results for an
individual device, the values given in this data sheet reflect sta-
tistical variations and worst cases. Consequently, it is not
meaningful to add parameters to derive longer times.
See Figure 30 on Page 41 under Test Conditions for voltage
reference levels.
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching charac-
teristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timing Requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
During processor reset (
RESET pin low) or software reset (SRST
bit in SYSCON register = 1), deassertion (
MS3–0, HBG,
DMAGx, RDx, WRx, CIF, PAGE, BRST) and three-state
(FLAG3-0, LxCLK, LxACK, LxDAT7-0, ACK, REDY,
PA,
TFSx, RFSx, TCLKx, RCLKx, DTx,
BMS, TDO, EMU,
DATA) timings differ. These occur asynchronously to CLKIN,
and may not meet the specifications published in the Timing
Requirements and Switching Characteristics tables. The
maximum delay for deassertion and three-state is one tCK from
RESET pin assertion low or setting the SRST bit in SYSCON.
During reset the DSP will not respond to
SBTS, HBR and MMS
accesses.
HBR asserted before reset will be recognized, but a
HBG will not be returned by the DSP until after reset is
deasserted and the DSP has completed bus synchronization.
Power-up Sequencing
For power-up sequencing, see Table 4 and Figure 6. During the
power-up sequence of the DSP, differences in the ramp-up rates
and activation time between the two power supplies can cause
current to flow in the I/O ESD protection circuitry. To prevent
this damage to the ESD diode protection circuitry, Analog
Devices, Inc. recommends including a bootstrap Schottky diode
(see Figure 7). The bootstrap Schottky diode connected between
the 1.9 V and 3.3 V power supplies protects the ADSP-21160N
from partially powering the 3.3 V supply. Including a Schottky
diode will shorten the delay between the supply ramps and thus
prevent damage to the ESD diode protection circuitry. With this
technique, if the 1.9 V rail rises ahead of the 3.3 V rail, the
Schottky diode pulls the 3.3 V rail along with the 1.9 V rail.
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參數(shù)描述
ADSP-21160NCE-100 制造商:Analog Devices 功能描述:
ADSP-21160NKB-100 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21160NKB-95 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21160NKB-X 制造商:Analog Devices 功能描述:
ADSP-21160NKBZ-100 功能描述:IC DSP CONTROLLER 32BIT 400-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
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