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| 型號(hào)： | ADSP-21065LKSZ-264 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLL 544KBIT 208-MQFP |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | 主機(jī)接口，串行端口 |
| 時(shí)鐘速率： | 60MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 64kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-MQFP（28x28） |
| 包裝： | 托盤 |
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REV. C
ADSP-21065L
–13–
POWER DISSIPATION ADSP-21065L
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note SHARC Power Dissipation Measurements.
Specifications are based on the following operating scenarios:
Table II. Internal Current Measurements
Peak Activity
High Activity
Operation
(IDDINPEAK)(IDDINHIGH)
Low Activity (IDDINLOW)
Instruction Type
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Core Memory Access
2 per Cycle (DM and PM)
1 per Cycle (DM)
None
Internal Memory DMA
1 per Cycle
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK
IDDINPEAK + %HIGH IDDINHIGH + %LOW IDDINLOW + %IDLE IDDIDLE = POWER CONSUMPTION
(See note 4 below Table III.)
IDDINPEAK + %HIGH IDDINHIGH + %LOW IDDINLOW + %IDLE16 IDDIDLE16 = POWER CONSUMPTION
(See note 5 below Table III.)
Table III. Internal Current Measurement Scenarios
Parameter
Test Conditions
Max
Unit
IDDINPEAK
Supply Current (Internal)
1
tCK = 33 ns, VDD = max
470
mA
tCK = 30 ns, VDD = max
510
mA
IDDINHIGH
Supply Current (Internal)
2
tCK = 33 ns, VDD = max
275
mA
tCK = 30 ns, VDD = max
300
mA
IDDINLOW
Supply Current (Internal)
3
tCK = 33 ns, VDD = max
240
mA
tCK = 30 ns, VDD = max
260
mA
IDDIDLE
Supply Current (IDLE)
4
tCK = 33 ns, VDD = max
150
mA
tCK = 30 ns, VDD = max
155
mA
IDDIDLE16
Supply Current (IDLE16)
5
VDD = max
50
mA
NOTES
1The test program used to measure I
DDINPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2I
DDINHIGH is a composite average based on a range of high activity code.
3I
DDINLOW is a composite average based on a range of low activity code.
4IDLE denotes ADSP-21065L state during execution of IDLE instruction.
5IDLE16 denotes ADSP-21065L state during execution of IDLE16 instruction.
TIMING SPECIFICATIONS
General Notes
Two speed grades of the ADSP-21065L are offered, 60 MHz and 66 MHz instruction rates. The specifications shown are based on a
CLKIN frequency of 30 MHz (tCK = 33.3 ns). The DT derating allows specifications at other CLKIN frequencies (within the min–
max range of the tCK specification; see Clock Input below). DT is the difference between the actual CLKIN period and a CLKIN
period of 33.3 ns:
DT = (tCK – 33.3)/32
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addi-
tion or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical varia-
tions and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times.
See Figure 27 in Equivalent Device Loading for AC Measurements (Includes All Fixtures) for voltage reference levels.
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