參數(shù)資料
型號(hào)： ADSP-21065LKSZ-264
廠商： Analog Devices Inc
文件頁數(shù)： 1/44頁
文件大?。?/td> 0K
描述： IC DSP CONTROLL 544KBIT 208-MQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 60MHz
非易失內(nèi)存： 外部
芯片上RAM： 64kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-MQFP（28x28）
包裝： 托盤
a
ADSP-21065L
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
2003 Analog Devices, Inc. All rights reserved.
REV. C
DSP Microcomputer
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC
)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I2S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
SPORT 1
4
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, TIMER
&
DATA BUFFERS
I/O PROCESSOR
INSTRUCTION
CACHE
32
48 BIT
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
BLOCK
0
BLOCK
1
JTAG
TEST &
EMULATION
7
HOST PORT
ADDR BUS
MUX
IOA
17
IOD
48
MULTIPROCESSOR
INTERFACE
DUAL-PORTED SRAM
EXTERNAL
PORT
DATA BUS
MUX
32
24
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
16
40 BIT
BARREL
SHIFTER
ALU
MULTIPLIER
32
48
40
CORE PROCESSOR
DMA
CONTROLLER
PROGRAM
SEQUENCER
DAG2
8
4
24
SDRAM
INTERFACE
(I2S)
(2 Rx, 2Tx)
(I2S)
SPORT 0
DAG1
8
4
32
DATA
ADDR
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
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