參數(shù)資料
型號: ADSP-21060CZ-133
廠商: Analog Devices Inc
文件頁數(shù): 39/64頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 240CQFP
產(chǎn)品培訓模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機接口,連接端口,串行端口
時鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 240-CBFQFP 裸露焊盤
供應商設(shè)備封裝: 240-CQFP(32x32)
包裝: 托盤
Rev. F
|
Page 44 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Figure 25. Serial Ports
DT
DRIVE EDGE
DRIVE
EDGE
DRIVE
EDGE
TCLK/RCLK
TCLK
(INT)
TCLK/RCLK
TCLK
(EXT)
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
DATA RECEIVE— INTERNAL CLOCK
DATA RECEIVE— EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
DATA TRANSMIT— INTERNAL CLOCK
DATA TRANSMIT— EXTERNAL CLOCK
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
tDDTTE
tDDTEN
tDDTTI
tDDTIN
tSDRI
tHDRI
tSFSI
tHFSI
tDFSE
tHOFSE
tSCLKIW
tSDRE
tHDRE
tSFSE
tHFSE
tDFSE
tSCLKW
tHOFSE
tDDTI
tHDTI
tSFSI
tHFSI
tSCLKIW
tDFSI
tHOFSI
tDDTE
tHDTE
tSFSE
tHFSE
tDFSE
tSCLKW
tHOFSE
CLKIN
tDPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
TCLK, RCLK
TFS, RFS, DT
TCLK (INT)
RCLK (INT)
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
tDCLK
LOW TO HIGH ONLY
tSTFSCK
CLKIN
tHTFSCK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O
FOR MESH MULTIPROCESSING.
TFS (EXT)
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