參數(shù)資料
型號: ADSP-21060CZ-133
廠商: Analog Devices Inc
文件頁數(shù): 15/64頁
文件大小: 0K
描述: IC DSP CONTROLLER 32BIT 240CQFP
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: 主機接口,連接端口,串行端口
時鐘速率: 33MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 240-CBFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 240-CQFP(32x32)
包裝: 托盤
Rev. F
|
Page 22 of 64
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March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Clock Input
Reset
Table 9. Clock Input
Parameter
ADSP-21060
ADSP-21062
40 MHz, 5 V
ADSP-21060
ADSP-21062
33 MHz, 5 V
ADSP-21060L
ADSP-21062L
40 MHz, 3.3 V
ADSP-21060L
ADSP-21062L
33 MHz, 3.3 V
Unit
MinMax
Min
Max
MinMax
Timing Requirements
tCK
CLKIN Period
25
100
30
100
25
100
30
100
ns
tCKL
CLKIN Width Low
7
8.75
ns
tCKH
CLKIN Width High
55
55ns
tCKRF
CLKIN Rise/Fall (0.4 V to 2.0 V)
3
ns
1 For the ADSP-21060LC, this specification is 9.5 ns min.
Figure 9. Clock Input
CLKIN
tCKH
tCKL
tCK
Table 10. Reset
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tWRST
RESET Pulse Width Low1
4tCK
ns
tSRST
RESET Setup Before CLKIN High2
14 + DT/2
tCK
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
2 Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-2106xs commu-
nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
Figure 10. Reset
CLKIN
RESET
tWRST
tSRST
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