參數(shù)資料
型號: ADS8323
元件分類: 其它接口
英文描述: TERMINAL
中文描述: IGBT模塊
文件頁數(shù): 9/16頁
文件大?。?/td> 272K
代理商: ADS8323
ADS8323
SBAS224B
9
www.ti.com
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CS
BYTE
RD
CONVST
CLOCK
DGND
+DV
DD
BUSY
D
D
D
D
D
D
D
D
Chip Select
Read Input
Conversion Start
Clock Input
Busy Output
+
Analog Input
9
10
11
12
13
14
15
16
R
O
R
I
N
N
+
D
A
I
I
32
31
30
29
0.1
μ
F
28
ADS8323
27
26
25
0.1
μ
F
10
μ
F
+
20pF
+5V Analog Supply
FIGURE 1. Typical Circuit Configuration.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS8323: single-ended or differential, as shown in Figures 2
and 3. When the input is single-ended, the
IN input is held
at the common-mode voltage. The +IN input swings around
the same common voltage and the peak-to-peak amplitude is
the (common-mode + V
REF
) and the (common-mode
V
REF
).
The value of V
REF
determines the range over which the
common-mode voltage may vary (see Figure 4).
ADS8323
ADS8323
Single-Ended Input
Common
Voltage
V
to +V
peak-to-peak
Differential Input
Common
Voltage
V
peak-to-peak
V
peak-to-peak
FIGURE 2. Methods of Driving the ADS8323 either Single-
Ended or Differential.
When the input is differential, the amplitude of the input is the
difference between the +IN and
IN input, or (+IN)
(
IN).
The peak-to-peak amplitude of each input is
±
1/2V
REF
around
this common voltage. However, since the inputs are 180
°
out-of-phase, the peak-to-peak amplitude of the differential
voltage is +V
REF
to
V
REF
. The value of V
REF
also determines
the range of the voltage that may be common to both inputs
(see Figure 5).
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and
IN inputs are
matched. If matching is not observed, it may result in offset
error, which changes with temperature. Often, a small capacitor
(20pF) between the positive and negative inputs helps to match
their impedance.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, and source imped-
ance. Essentially, the current into the ADS8323 charges the
internal capacitor array during the sampling period. After this
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (25pF) to a 16-bit settling
level within 4 clock cycles (400ns), if the minimum acquisition
time is used. When the converter goes into the hold mode,
the input impedance is greater than 1G
.
Care must be taken regarding the absolute analog input
voltage. The +IN and
IN inputs should always remain within
the range of AGND
0.3V to AV
DD
+ 0.3V.
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