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| 型號(hào)： | ADS8323 |
| 元件分類： | 其它接口 |
| 英文描述： | TERMINAL |
| 中文描述： | IGBT模塊 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | ADS8323 |
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ADS8323
SBAS224B
12
www.ti.com
START OF A CONVERSION AND READING DATA
By bringing the CONVST signal LOW, the input data is
immediately placed in the hold mode (10ns). Although CS
must be LOW when CONVST goes LOW to initiate a conver-
sion. The conversion follows with the next rising edge of
CLOCK. If it is important to detect a hold command during a
certain clock cycle, then the falling edge of the CONVST
signal must occur at least 10ns before the rising edge of
CLOCK (see Timing Diagram, t
D1
). The CONVST signal can
remain LOW without initiating a new conversion. The CONVST
signal must be HIGH for at least 20ns (see Timing Diagram,
t
W4
) before it is brought LOW again and CONVST must stay
LOW for at least 20ns (see Timing Diagram, t
W3
). Once a
CONVST signal goes LOW, further impulses of this signal
are ignored until the conversion is finished or the part is
reset.
When the conversion is finished (after 16 clock cycles) the
sampling switches will close and sample the new value. The
start of the next conversion must be delayed to allow the
input capacitor of the ADS8323 to be fully charged. This
delay time depends on the driving amplifier, but should be at
least 400ns. To gain acquisition time, the falling edge of
CONVST must take place just before the rising edge of
CLOCK (see Timing Diagram, t
D1
). One conversion cycle
requires 20 clock cycles. However, reading data during the
conversion or on a falling hold edge might cause a loss in
performance.
Reading Data (RD, CS)
—
In general, the data outputs are in
tri-state. Both CS and RD must be LOW to enable these
outputs. RD and CS must stay LOW together for at least
40ns (see Timing Diagram, t
D7
) before the output data is
valid. RD must remain HIGH for at least 20ns (see Timing
Diagram, t
W7
) before bringing it back LOW for a subsequent
read command. 16 clock-cycles after the start of a conver-
sion (next rising edge of clock after the falling edge of
CONVST), the new data is latched into the output register
and the reading process can start again.
CS being LOW tells the ADS8323 that the bus on the board
is assigned to the ADS8323. If an ADC shares a bus with
digital gates, there is a possibility that digital (high-frequency)
noise gets coupled into the ADC. If the bus is just used by the
ADS8323, CS can be hard-wired to ground. The output data
should not be read 125ns prior to the falling edge of CONVST
and 10ns after the falling edge.
The ADS8323
’
s output is in Binary Two
’
s Complement for-
mat (see Figure 8).
DESCRIPTION
ANALOG VALUE
Full-Scale Range
2
V
REF
Least Significant
Bit (LSB)
2
V
REF
/65535
BINARY CODE
HEX CODE
+Full Scale
+V
REF
–
1 LSB
0111 1111 1111 1111
7FFF
Midscale
0V
0000 0000 0000 0000
0000
Midscale
–
1LSB
0V
–
1 LSB
1111 1111 1111 1111
FFFF
Zero
–
V
REF
1000 0000 0000 0000
8000
DIGITAL OUTPUT
BINARY TWO
’
S COMPLEMENT
TABLE I. Ideal Input Voltages and Output Codes.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8323 circuitry. This is particularly
true if the CLOCK input is approaching the maximum through-
put rate.
As the ADS8323 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch-
ing speed, the more difficult it will be to achieve good
performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n
“
windows
”
in which large external transient voltages can affect the
conversion result. Such glitches might originate from switch-
ing power supplies, nearby digital logic, or high-power de-
vices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the external
event. Their error can change if the external event changes
in time with respect to the CLOCK input.
On average, the ADS8323 draws very little current from an
external reference as the reference voltage is internally
buffered. If the reference voltage is external and originates
from an op amp, make sure that it can drive the bypass
capacitor or capacitors without oscillation. A 0.1
μ
F bypass
capacitor is recommended from pin 31 directly to ground.
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the
“
analog
”
ground.
Avoid connections which are too close to the grounding point
of a microcontroller or digital signal processor. If required, run
a ground trace directly from the converter to the power-
supply entry point. The ideal layout will include an analog
ground plane dedicated to the converter and associated
analog circuitry.
As with the GND connections, V
DD
should be connected to a
+5V power supply plane, or trace, that is separate from the
connection for digital logic until they are connected at the
power entry point. Power to the ADS8323 should be clean
and well bypassed. A 0.1
μ
F ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1
μ
F to 10
μ
F capacitor is recommended. If needed, an even
larger capacitor and a 5
or 10
series resistor may be used
to low-pass filter a noisy supply. In some situations, addi-
tional bypassing may be required, such as a 100
μ
F electro-
lytic capacitor, or even a Pi filter made up of inductors and
capacitors all designed to essentially low-pass filter the +5V
supply, removing the high-frequency noise.
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參數(shù)描述 |
|---|---|
| ADS8323EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS8323 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8323Y | 制造商:Texas Instruments 功能描述:IC 16BIT ADC SMD 8323 TQFP32 制造商:Texas Instruments 功能描述:IC, 16BIT ADC, SMD, 8323, TQFP32 制造商:Texas Instruments 功能描述:IC, 16BIT ADC, SMD, 8323, TQFP32; Resolution (Bits):16bit; Sampling Rate:500kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:17mA; Digital IC Case Style:TQFP; No. of Pins:32; Input ;RoHS Compliant: Yes |
| ADS8323Y | 制造商:Texas Instruments 功能描述:IC 16BIT ADC SMD 8323 TQFP32 |
| ADS8323Y/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Pseudo Bipolar 16-Bit 500kSPS CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8323Y/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Pseudo Bipolar 16-Bit 500kSPS CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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