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參數(shù)資料
| 型號(hào)： | ADS8323 |
| 元件分類： | 其它接口 |
| 英文描述： | TERMINAL |
| 中文描述： | IGBT模塊 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | ADS8323 |
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ADS8323
SBAS224B
8
www.ti.com
THEORY OF OPERATION
The ADS8323 is a high-speed Successive Approximation
Register (SAR) 16-bit ADC with an internal 2.5V bandgap
reference that operates from a single +5V supply. The input
is fully differential with a typical common-mode rejection of
70dB. The part accepts a differential analog input voltage in
the range of
–
V
REF
to +V
REF
, centered on the common-mode
voltage (see the Analog Input section). The part will also
accept bipolar input ranges when a level shift circuit is used
at the front end (see Figure 7). See Figure 1 for the basic
operating circuit for the ADS8323.
The ADS8323 requires an external clock to run the conver-
sion process. This clock can vary between 25kHz (1.25kHz
throughput) and 10MHz (500kSPS throughput). The duty
cycle of the clock is unimportant as long as the minimum
HIGH and LOW times are at least 40ns and the clock period
is at least 100ns. The minimum clock frequency is governed
by the parasitic leakage of the Capacitive Digital-to-Analog
Converter (CDAC) capacitors internal to the ADS8323.
The analog input is provided to two input pins, +IN and
–
IN.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. A conversion
is initiated on the ADS8323 by bringing CONVST (pin 21)
LOW for a minimum of 20ns. CONVST LOW places the
sample-and-hold amplifier in the hold state and the conver-
sion process is started. The BUSY output (pin 17) will go
HIGH when the conversion begins and will stay HIGH during
the conversion. While a conversion is in progress, both
inputs are disconnected from any internal function. When the
conversion result is latched into the output register, the
BUSY signal will go LOW. The data can be read from the
parallel output bus following the conversion by bringing both
RD and CS LOW.
NOTE: This mode of operation is described in more detail in
the Timing and Control section of this data sheet.
SAMPLE-AND-HOLD SECTION
The sample-and-hold on the ADS8323 allow the ADC to
accurately convert an input sine wave of full-scale amplitude
to 16-bit resolution. The input bandwidth of the sample-and-
hold is greater than the Nyquist rate (Nyquist equals one-half
of the sampling rate) of the ADC even when the ADC is
operated at its maximum throughput rate of 500kSPS. The
typical small-signal bandwidth of the sample-and-hold ampli-
fier is 20MHz. Typical aperture delay time, or the time it takes
for the ADS8323 to switch from the sample to the hold mode
following the negative edge of the CONVST signal, is 10ns.
The average delta of repeated aperture delay values is typi-
cally 30ps (also known as aperture jitter). These specifications
reflect the ability of the ADS8323 to capture AC input signals
accurately at the exact same moment in time.
REFERENCE
If the internal reference is used, REF
OUT
(pin 32) should be
directly connected to REF
IN
(pin 31). The ADS8323 can
operate, however, with an external reference in the range of
1.5V to 2.55V for a corresponding full-scale range of 3.0V to
5.1V. The internal reference of the ADS8323 is double-
buffered. If the internal reference is used to drive an external
load, a buffer is provided between the reference and the load
applied to REF
OUT
(pin 32) (the internal reference can typi-
cally source or sink 10
μ
A of current; compensation capaci-
tance should be at least 0.1
μ
F to minimize noise). If an
external reference is used, the second buffer provides isola-
tion between the external reference and the CDAC. This
buffer is also used to recharge all of the capacitors of the
CDAC during conversion.
TYPICAL CHARACTERISTICS
(Cont.)
At
–
40
°
C to +85
°
C, +DV
DD
= +AV
DD
= +5V, V
REF
= +2.5V, f
SAMPLE
= 500kSPS, and f
CLK
= 20
f
SAMPLE
, unless otherwise specified.
NEGATIVE FULL-SCALE vs TEMPERATURE
Temperature (
°
C)
–
40
–
20
0
20
40
60
80
100
D
D
μ
V
1
0
–
1
–
2
–
3
–
4
–
5
76.3
0
–
76.3
–
152.6
–
228.9
–
305.2
–
381.5
4
3
2
1
0
–
1
–
2
–
3
–
4
I
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
0000
H
2000
H
4000
H
6000
H
8000
H
Decimal Code
A000
H
C000
H
E000
H
FFFF
H
2.5
2.0
1.5
1.0
0.5
0.0
–
0.5
–
1.0
–
1.5
D
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PDF描述 |
|---|---|
| ADS8343 | 16-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS8343E | 16-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS8343EB | 16-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8323EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 ADS8323 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8323Y | 制造商:Texas Instruments 功能描述:IC 16BIT ADC SMD 8323 TQFP32 制造商:Texas Instruments 功能描述:IC, 16BIT ADC, SMD, 8323, TQFP32 制造商:Texas Instruments 功能描述:IC, 16BIT ADC, SMD, 8323, TQFP32; Resolution (Bits):16bit; Sampling Rate:500kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:17mA; Digital IC Case Style:TQFP; No. of Pins:32; Input ;RoHS Compliant: Yes |
| ADS8323Y | 制造商:Texas Instruments 功能描述:IC 16BIT ADC SMD 8323 TQFP32 |
| ADS8323Y/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Pseudo Bipolar 16-Bit 500kSPS CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8323Y/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Pseudo Bipolar 16-Bit 500kSPS CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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