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參數(shù)資料
| 型號： | ADS8323 |
| 元件分類： | 其它接口 |
| 英文描述： | TERMINAL |
| 中文描述： | IGBT模塊 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 272K |
| 代理商： | ADS8323 |
ADS8323
SBAS224B
11
www.ti.com
NOISE
Figure 6 shows the transition noise of the ADS8323. A low-
level DC input was applied to the analog-input pins and the
converter was put through 8192 conversions. The digital
output of the ADC will vary in output code due to the internal
noise of the ADS8323. This is true for all 16-bit SAR-type
ADCs. The ADS8323, with five output codes for the
σ
distribu-
tion, will yield a <
±
0.8LSB transition noise at 5V operation.
Remember that to achieve this low-noise performance, the
peak-to-peak noise of the input signal and reference must be
< 50
μ
V.
DIGITAL INTERFACE
TIMING AND CONTROL
See the timing diagram in the Timing Characteristics section for
detailed information on timing signals and their requirements.
The ADS8323 uses an external clock (CLOCK, pin 20) that
controls the conversion rate of the CDAC. With a 10MHz
external clock, the ADC sampling rate is 500kSPS that
corresponds to a 2
μ
s maximum throughput time.
EXPLANATION OF CLOCK, BUSY AND BYTE PINS
CLOCK
—
An external clock must be provided for the
ADS8323. The maximum clock frequency is 10MHz and that
provides 500kSPS throughput. The minimum clock frequency
is 25kHz and that provides 1.25kHz throughput. The mini-
mum clock cycle is 100ns (see Timing Diagram, t
C1
), and
CLOCK must remain HIGH (see Timing Diagram, t
W1
) or
LOW (see Timing Diagram, t
W2
) for at least 40ns.
BUSY
—
Initially BUSY output is LOW. Reading data from
output register or sampling the input analog signal will not
affect the state of the BUSY signal. After the CONVST input
goes LOW and conversion starts, a maximum of 25ns later
the BUSY output will go HIGH. That signal will stay HIGH
during conversion and will provide the status of the internal
ADC to the DSP or uC. At the end of conversion, on the rising
edge of 17th clock cycle, new data from the internal ADC is
latched into the output registers. The BUSY signal will go
LOW a maximum of 25ns later (see Timing Diagram, t
D4
).
BYTE
—
The output data will appear as a full 16-bit word on
DB15-DB0 (MSB-LSB or D15-D0) if BYTE is LOW. If there is
only an 8-bit bus available on a board, the result may also be
read on an 8-bit bus by using only DB7-DB0. In this case, two
reads are necessary (see Timing Diagram). The first, as
before, leaving BYTE LOW and reading the 8 least significant
bits on DB7-DB0, then bringing BYTE HIGH. When BYTE is
HIGH, the upper 8 bits (D15-D8) will appear on DB7-DB0.
5052
Code
0015
0014
0018
0017
0016
300
54
1968
818
FIGURE 6. Histogram of 8192 Conversions of a Low-Level
DC Input.
AVERAGING
Averaging the digital codes can compensate the noise of the ADC.
By averaging conversion results, transition noise will be reduced by
a factor of 1/
√
n, where n is the number of averages. For example,
averaging 4 conversion results will reduce the transition noise by
1/2 to
±
0.4LSB. Averaging should only be used for input signals
with frequencies near DC. For AC signals, a digital filter can be
used to low-pass filter and decimate the output codes. This works
in a similar manner to averaging
—
for every decimation by 2, the
signal-to-noise ratio will improve 3dB.
BIPOLAR INPUTS
The differential inputs of the ADS8323 were designed to accept
bipolar inputs (
–
V
REF
and +V
REF
) around the common-mode
voltage, which corresponds to a 0V to 5V input range with a
2.5V reference. By using a simple op amp circuit featuring four
high-precision external resistors, the ADS8323 can be config-
ured to accept bipolar inputs. The conventional
±
2.5V,
±
5V, and
±
10V input ranges could be interfaced to the ADS8323 using
the resistor values shown in Figure 7.
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
R
1
R
2
+IN (pin 26)
–
IN (pin 25)
REF
OUT
(pin 32)
2.5V
4k
20k
Bipolar
Input
BIPOLAR INPUT
±
10V
±
5V
±
2.5V
R
1
1k
2k
4k
R
2
5k
10k
20k
OPA132
ADS8323
OPA353
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8323EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS8323 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8323Y | 制造商:Texas Instruments 功能描述:IC 16BIT ADC SMD 8323 TQFP32 制造商:Texas Instruments 功能描述:IC, 16BIT ADC, SMD, 8323, TQFP32 制造商:Texas Instruments 功能描述:IC, 16BIT ADC, SMD, 8323, TQFP32; Resolution (Bits):16bit; Sampling Rate:500kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:17mA; Digital IC Case Style:TQFP; No. of Pins:32; Input ;RoHS Compliant: Yes |
| ADS8323Y | 制造商:Texas Instruments 功能描述:IC 16BIT ADC SMD 8323 TQFP32 |
| ADS8323Y/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Pseudo Bipolar 16-Bit 500kSPS CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8323Y/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Pseudo Bipolar 16-Bit 500kSPS CMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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