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參數(shù)資料
| 型號(hào)： | ADS7862 |
| 英文描述： | CMOS 4-Bit-by-16-Word FIFO Register 16-CDIP -55 to 125 |
| 中文描述： | 雙為500kHz，12位，2通道同步采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 13/13頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | ADS7862 |
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13
ADS7862
SECTION A
Conversions are initiated by bringing the CONVST pin (pin
18) LOW for a minimum of 5ns (after the 5ns minimum
requirement has been met, the CONVST pin can be brought
HIGH). The ADS7862 will switch from the sample to the
hold mode on the falling edge of the CONVST command.
Following the first rising edge of the external clock after a
CONVST LOW, the ADS7862 will begin conversion (this
first rising edge of the external clock represents the start of
clock cycle one; the ADS7862 requires sixteen cycles to
complete a conversion). The input channel is also latched in
at this point in time. The A0 input (pin 22) must be selected
250ns prior to the CONVST pin going LOW so that the
correct address will be selected prior to conversion. The
BUSY output will go HIGH immediately following CONVST
going LOW. BUSY will stay HIGH through the conversion
process and return LOW when the conversion has ended.
After CONVST has remained LOW for the minimum time,
the ADS7862 will switch from the hold mode to the conver-
sion mode synchronous to the next rising edge of the
external clock and conversion ‘n – 2’ will begin. Both RD
(pin 21) and CS (pin 20) can be HIGH during and before a
conversion. However, they must both be LOW to enable the
output bus and read data out.
SECTION B
The CONVST pin is switched from HIGH to LOW a second
time to initiate conversion ‘n – 1’. Again, the address must be
selected 250ns prior to CONVST going LOW to ensure that
the new address is selected for conversion. Both the RD and
CS pins are brought LOW in order to enable the parallel output
bus with the ‘n – 2’ conversion results of Channel A0. While
continuing to hold CS LOW, RD is held LOW for a minimum
of 30ns which enables the output bus with the Channel A0
results of conversion ‘n – 2’. The RD pin is toggled from
HIGH to LOW a second time in order to enable the output bus
with the Channel B0 results of conversion ‘n – 2’.
SECTION C
CONVST is brought LOW for a third time to initiate
conversion ‘n’ (Channel 0). While the conversion is in
process, the results for both conversions ‘n – 2’ and ‘n – 1’
can be read. The address pin is brought HIGH while CS and
RD are brought LOW which enables the output bus with the
Channel A1 results of conversion ‘n – 1’. The RD pin is
toggled from HIGH to LOW for a second time in Section C
and the ‘n – 1’ conversion results for Channel B1 appear at
the output bus. The address pin (A0) is then brought LOW
and the read process repeats itself with the most recent
conversion results for Channel 0 (n – 2) appearing at the
output bus.
READING DATA
The ADS7862 outputs full parallel data in Binary Two’s
Complement data output format. The parallel output will be
active when CS (pin 20) and RD (pin 21) are both LOW. The
output data should not be read 125ns prior to the falling edge
of CONVST and 10ns after the falling edge. Any other
combination of CS and RD will tri-state the parallel output.
Valid conversion data can be read on pins 5 through 16
(MSB-LSB). Refer to Table I for ideal output codes.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7862 circuitry. This is particu-
larly true if the CLOCK input is approaching the maximum
throughput rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conver-
sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver-
sion result. Such glitches might originate from switching
power supplies, nearby digital logic or high power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter-
nal event. Their error can change if the external event
changes in time with respect to the CLOCK input.
With this in mind, power to the ADS7862 should be clean
and well bypassed. A 0.1
μ
F ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1
μ
F to 10
μ
F capacitor is recommended. If needed, an even
larger capacitor and a 5
or 10
series resistor may be used
to low-pass filter a noisy supply. On average, the ADS7862
draws very little current from an external reference as the
reference voltage is internally buffered. If the reference
voltage is external and originates from an op amp, make sure
that it can drive the bypass capacitor or capacitors without
oscillation. A bypass capacitor is not necessary when using
the internal reference (tie pin 1 directly to pin 2).
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the ‘a(chǎn)nalog’
ground. Avoid connections which are too close to the ground-
ing point of a microcontroller or digital signal processor. If
required, run a ground trace directly from the converter to
the power supply entry point. The ideal layout will include
an analog ground plane dedicated to the converter and
associated analog circuitry.
APPLICATIONS
An applications section will be added featuring the ADS7862
interfacing to popular DSP processors. The updated data
sheet will be available in the near future on the Burr-Brown
web site:
http: //www.burr-brown.com/
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS7862Y | Dual 500kHz, 12-Bit, 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7862YB | CMOS Hex Schmitt Triggers 14-PDIP -55 to 125 |
| ADS7870 | 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM |
| ADS7870EA | 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM |
| ADS7891 | CMOS Hex Schmitt Triggers 14-SO -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7862Y | 制造商:BB 制造商全稱(chēng):BB 功能描述:Dual 500kHz, 12-Bit, 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7862Y/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7862Y/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7862Y/2K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7862Y/2KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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