參數(shù)資料
型號(hào)： ADS7862
英文描述： CMOS 4-Bit-by-16-Word FIFO Register 16-CDIP -55 to 125
中文描述： 雙為500kHz，12位，2通道同步采樣模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 12/13頁(yè)
文件大?。?/td> 159K
代理商： ADS7862
12
ADS7862
NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
HIGH to LOW in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
CLOCK
CONVST
Cycle 1
Cycle 2
t
CKP
125ns
10ns
5ns
10ns
5ns
A
B
C
FIGURE 10. Timing Between CLOCK and CONVST to Start a Conversion.
FIGURE 11. ADS7862 Timing Diagram Showing Complete Functionality.
1
1
1
SECTION A
CLOCK
CONVST
A0
RD
CS
DATA
BUSY
TIME 0
1
μ
2
μ
3
μ
4
μ
5
μ
min 250ns
SECTION B
SECTION C
ChA0
ChB0
Time (seconds)
ChA1
ChA0
4 Output-Register
Data of Ch0 Still Stored
A0 Selects Between
Ch0 and Ch1 at Output
Conversion of Ch0
Low Data Level
Tri-state of Output
Conversion of Ch0
High Data Level
Output Active
16
16
A0 = 1
Conversion of Ch1
min 250ns
CS Needed Only During Reading
Conversion of Ch1
ChB0
ChB1
A0 = 0 Conversion of Ch0
A0 = 0
Conversion of Ch0
1st RD After CONVST
ChA at Output
2nd RD After CONVST
ChB at Output
相關(guān)PDF資料
PDF描述
ADS7862Y Dual 500kHz, 12-Bit, 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
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ADS7870 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM
ADS7870EA 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS7862Y 制造商:BB 制造商全稱(chēng):BB 功能描述:Dual 500kHz, 12-Bit, 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
ADS7862Y/250 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7862Y/250G4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7862Y/2K 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7862Y/2KG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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