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參數(shù)資料
| 型號： | ADS7862 |
| 英文描述： | CMOS 4-Bit-by-16-Word FIFO Register 16-CDIP -55 to 125 |
| 中文描述： | 雙為500kHz，12位，2通道同步采樣模擬到數(shù)字轉換器 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大小： | 159K |
| 代理商： | ADS7862 |
10
ADS7862
Three timing diagrams are used to explain the operation of
the ADS7862. Figure 8 shows the timing relationship be-
tween the CLOCK, CONVST (pin 18) and the conversion
Code (decimal)
8000
7000
6000
5000
4000
3000
2000
1000
0
N
2044
2045
2046
2047
2048
FIGURE 5. Histogram of 8,000 Conversions of a DC Input.
FIGURE 6. Test Circuits for Timing Specifications.
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
FIGURE 8. Conversion Mode.
TRANSITION NOISE
Figure 5 shows a histogram plot for the ADS7862 following
8,000 conversions of a DC input. The DC input was set at
output code 2046. All but one of the conversions had an
output code result of 2046 (one of the conversions resulted
in an output of 2047). The histogram reveals the excellent
noise performance of the ADS7862.
BIPOLAR INPUTS
The differential inputs of the ADS7862 were designed to
accept bipolar inputs (–V
REF
and +V
REF
) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resis-
tors, the ADS7862 can be configured to except bipolar
inputs. The conventional
±
2.5V,
±
5V, and
±
10V input
ranges can be interfaced to the ADS7862 using the resistor
values shown in Figure 7.
TIMING AND CONTROL
The ADS7862 uses an external clock (CLOCK, pin 19)
which controls the conversion rate of the CDAC. With an
8MHz external clock, the A/D sampling rate is 500kHz
which corresponds to a 2
μ
s maximum throughput time.
DATA
1.4V
Test Point
3k
100pF
C
LOAD
t
R
DATA
Voltage Waveforms for DATA Rise and Fall Times t
R
, and t
F
.
V
OH
V
OL
t
F
R
1
R
2
+IN
–IN
REF
OUT
(pin 2)
2.5V
4k
20k
Bipolar Input
BIPOLAR INPUT
±
10V
±
5V
±
2.5V
R
1
1k
2k
4k
R
2
5k
10k
20k
OPA132
ADS7862
CONVST
CONVERSION
MODE
SAMPLE
HOLD
CONVERT
CLOCK
t
CKH
t
CKP
t
3
t
CKL
NOTE: The ADS7862 will switch from the sample to the hold mode the instant CONVST goes LOW regardless of
the state of the external clock. The conversion process is initiated with the first rising edge of the external clock
following CONVST going LOW.
相關PDF資料 |
PDF描述 |
|---|---|
| ADS7862Y | Dual 500kHz, 12-Bit, 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7862YB | CMOS Hex Schmitt Triggers 14-PDIP -55 to 125 |
| ADS7870 | 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM |
| ADS7870EA | 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM |
| ADS7891 | CMOS Hex Schmitt Triggers 14-SO -55 to 125 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7862Y | 制造商:BB 制造商全稱:BB 功能描述:Dual 500kHz, 12-Bit, 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS7862Y/250 | 功能描述:模數(shù)轉換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7862Y/250G4 | 功能描述:模數(shù)轉換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7862Y/2K | 功能描述:模數(shù)轉換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7862Y/2KG4 | 功能描述:模數(shù)轉換器 - ADC Dual 500kHz 12-Bit 2+2 Ch Sim Smpl ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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