參數資料
型號: ADS5521IPAPR
英文描述: 12-Bit, 105MSPS Analog-toDigital Converter
中文描述: 12位,105Msps模數轉換器toDigital轉換器
文件頁數: 9/20頁
文件大?。?/td> 261K
代理商: ADS5521IPAPR
SBAS309 MAY 2004
www.ti.com
9
PIN ASSIGNMENTS
TERMINAL
NO.
NAME
AVDD
NO.
OF PINS
12
I/O
I
DESCRIPTION
5, 7, 9, 15, 22, 24, 26,
28, 33, 34, 37, 39
Analog power supply
AGND
6, 8, 12, 13, 14, 16, 18,
21, 23, 25, 27, 32, 36, 38
14
I
Analog ground
DRVDD
DRGND
49, 58
2
I
Output driver power supply
1, 42, 48,
50, 57, 59
6
I
Output driver ground
NC
44, 45
2
Not connected
INP
19
1
I
Differential analog input (positive)
INM
20
1
I
Differential analog input (negative)
REFP
29
1
O
Reference voltage (positive); 0.1
μ
F capacitor in series with a 1
resistor to GND
REFM
30
1
O
Reference voltage (negative); 0.1
μ
F capacitor in series with a 1
resistor to GND
IREF
31
1
I
Current set; 56k
resistor to GND; do not connect capacitors
CM
17
1
O
Common-mode output voltage
RESET
35
1
I
Reset (active high), 200k
resistor to AVDD
Output enable (active high)
Data format and clock out polarity select(1)
OE
41
1
I
DFS
40
1
I
CLKP
10
1
I
Data converter differential input clock (positive)
CLKM
11
1
I
Data converter differential input clock (negative)
SEN
4
1
I
Serial interface chip select
SDATA
3
1
I
Serial interface data
SCLK
2
1
I
Serial interface clock
D0 (LSB)D11 (MSB)
46, 47, 5156, 6063
12
O
Parallel data output
OVR
64
1
O
Over-range indicator bit
CLKOUT
43
1
O
CMOS clock out in sync with data
NOTE:PowerPAD is connected to analog ground.
(1)The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AVDD, 5/8 AVDD, and AVDD. The thresholds are centered. More details are
listed in Table 3 on page 8.
P
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