參數(shù)資料
型號: ADS5521IPAPR
英文描述: 12-Bit, 105MSPS Analog-toDigital Converter
中文描述: 12位,105Msps模數(shù)轉(zhuǎn)換器toDigital轉(zhuǎn)換器
文件頁數(shù): 12/20頁
文件大?。?/td> 261K
代理商: ADS5521IPAPR
SBAS309 MAY 2004
www.ti.com
12
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5521 is a low-power, 12-bit, 105MSPS,
CMOS, switched capacitor, pipeline ADC that operates
from a single 3.3V supply. The conversion process is
initiated by a falling edge of the external input clock.
Once the signal is captured by the input S&H, the input
sample is sequentially converted by a series of small
resolution stages, with the outputs combined in a digital
correction logic block.
Both the rising and the falling
clock edges are used to propagate the sample through
the pipeline every half clock cycle. This process results
in a data latency of 16.5 clock cycles, after which the
output data is available as a 12-bit parallel word, coded
in either straight offset binary or binary two’s
complement format.
INPUT CONFIGURATION
The analog input for the ADS5521 consists of a
differential sample-and-hold architecture implemented
using a switched capacitor technique, shown in
Figure 4.
R
3
R
1a
L
1
L
1
, L
2
: 6nh to 10nh effective
R
1a
, R
1b
: 25
to 35
C
1a
, C
1b
: 2.2pF to 2.6pF
CP
1
, CP
2
: 2.5pF to 3.5pF
CP
3
, CP
4
, : 1.2pF to 1.8pF
C
ACROSS
: 0.8pF to 1.2pF
R
to 120
Switches:
W
1a
, W
: On Resistance: 25
to 35
W
2
: On Resistance: 7.5
to 15
W
3a
, W
3b
: On Resistance: 40
to 60
W
1a
, W
1b
, W
2
, W
3a
, W
3b
: Off Resistance: 1e10
All switches are on in sample phase.
Approximately half of every clock period is a sample phase.
W
1a
W
2
W
1b
L
2
R
1b
C
1a
C
1b
C
ACROSS
SAMPLE
PHASE
SAMPLE
PHASE
SWITCH
S
S
S
SAMPLE
PHASE
CP
1
CP
3
VINCM
1V
CP
4
W
3a
SAMPLE
PHASE
CP
2
W
3a
SAMPLE
PHASE
INP
INM
Figure 4. Analog Input Stage
P
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