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參數(shù)資料
| 型號： | ADS5521IPAPR |
| 英文描述： | 12-Bit, 105MSPS Analog-toDigital Converter |
| 中文描述： | 12位，105Msps模數(shù)轉(zhuǎn)換器toDigital轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 261K |
| 代理商： | ADS5521IPAPR |
SBAS309 MAY 2004
www.ti.com
6
TIMING CHARACTERISTCS
16.5 Clock Cycles
Input Clock
Output Clock
Data Out
(D0D11)
Analog
Input
Signal
Sample
N
N + 1
N + 2
N + 3
N + 4
N + 15
N + 16
N + 17
N
17
N
16
N
15
N
13
N
3
N
2
N
1
N
t
A
t
SETUP
t
HOLD
Data Invalid
t
PDI
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
Typ, min, and max values at TA = +25
°
C, full temperature range is TMIN = 40
°
C to tMAX = +85
°
C, sampling rate = 105MSPS, 50% clock duty
cycle, AVDD = DRVDD = 3.3V, DLL On, 1dBFS differential input, and 3VPP differential clock, unless otherwise noted.
PARAMETER
Switching Specification
Aperture delay, tA
Aperture jitter (uncertainty)
Data setup time, tSETUP
Data hold time, tHOLD
DESCRIPTION
MIN
TYP
MAX
UNIT
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid to 50% of CLKOUT rising edge
CLKOUT rising edge to data becoming invalid
Input clock falling edge (on which sampling
takes place) to input clock rising edge (on
which the corresponding data is given out)
Input clock rising edge to data valid
Data out 20% to 80%
Data out 80% to 20%
1
ns
fs
ns
ns
300
TBD
TBD
Data latency, tD(Pipe)
16.5
Clock Cycles
Propagation delay, tPDI
Data rise time
Data fall time
Output enable (OE) to
output stable delay
TBD
2.5
2.5
ns
ns
ns
2
ms
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK
when SEN is active.
Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
Minimum width of data stream for a valid loading is
16 clocks.
Data is loaded at every 16th SCLK falling edge
while SEN is low.
In case the word length exceeds a multiple of 16
bits, the excess bits are ignored.
Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
P
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS5521IPAPRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 105MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5522 | 制造商:BB 制造商全稱:BB 功能描述:14-Bit, 80MSPS Analog-to-Digital Converter |
| ADS5522EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS5522 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS5522IPAP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 80MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5522IPAPG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 80MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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