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參數(shù)資料
| 型號： | ADS5521IPAPR |
| 英文描述： | 12-Bit, 105MSPS Analog-toDigital Converter |
| 中文描述： | 12位，105Msps模數(shù)轉(zhuǎn)換器toDigital轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 261K |
| 代理商： | ADS5521IPAPR |
SBAS309 MAY 2004
www.ti.com
15
POWER SUPPLY SEQUENCE
The ADS5521 requires a power-up sequence where the
DRV
DD
supply must be at least 0.4V by the time the
AV
DD
supply reaches 3.0V. Powering up both supplies
at the same time will work without any problem. If this
sequence is not followed, the device may stay in
power-down mode.
POWER DOWN
The device will enter power-down in one of two ways:
either by reducing the clock speed to between DC and
1MHz, or by setting a bit through the serial
programming interface. Using the reduced clock speed,
the power-down may be initiated for clock frequencies
below 10MHz. For clock frequencies between 1MHz
and 10Mhz, this can vary from device to device, but will
power-down for clock speeds below 1MHz.
The device can be powered down by programming the
internal register (see
Serial Programming Interface
section). The outputs become tri-stated and only the
internal reference is powered up to shorten the
power-up time. The Power-Down mode reduces power
dissipation to a minimum of 180mW.
REFERENCE CIRCUIT
The ADS5521 has built-in internal reference
generation, requiring no external circuitry on the printed
circuit board (PCB). For optimum performance, it is best
to connect both REFP and REFM to ground with a 1
μ
F
decoupling capacitor in series with a 1
resistor, as
shown in Figure 8. In addition, an external 56.2k
resistor should be connected from IREF (pin 31) to
AGND to set the proper current for the operation of the
ADC, as shown in Figure 8. No capacitor should be
connected between pin 31 and ground; only the 56.2k
resistor should be used.
29
30
31
REFP
REFM
IREF
56k
1
μ
F
1
μ
F
1
1
Figure 8. REFP, REFM, and IREF Connections for
Optimum Performance
CLOCK INPUT
The ADS5521 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. The common-mode voltage of the clock
inputs is set internally to CM (pin 17) using internal 5k
resistors that connect CLKP (pin 10) and CLKM (pin 11)
to CM (pin 17), as shown in Figure 9.
5k
5k
CLKM
CLKP
CM
CM
6pF
3pF
3pF
Figure 9. Clock Inputs
When driven with a single-ended CMOS clock input, it
is best to connect CLKM (pin 11) to ground with a
0.01
μ
F capacitor, while CLKP is AC-coupled with a
0.01
μ
F capacitor to the clock source, as shown in
Figure 10.
0.01
μ
F
0.01
μ
F
CLKP
ADS5521
CLKM
Square Wave
or Sine Wave
(3V
PP
)
Figure 10. AC-Coupled, Single-Ended Clock Input
The ADS5521 clock input can also be driven
differentially, reducing susceptibility to common-mode
noise. In this case, it is best to connect both clock inputs
to the differential input clock signal with 0.01
μ
F
capacitors, as shown in Figure 11.
P
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS5521IPAPRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 105MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5522 | 制造商:BB 制造商全稱:BB 功能描述:14-Bit, 80MSPS Analog-to-Digital Converter |
| ADS5522EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS5522 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS5522IPAP | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 80MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS5522IPAPG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 80MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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