參數(shù)資料
型號(hào): ADP5042ACPZ-2-R7
廠商: Analog Devices Inc
文件頁數(shù): 7/32頁
文件大?。?/td> 1378K
描述: IC REG TRPL BCK/LINEAR 20LFCSP
標(biāo)準(zhǔn)包裝: 1
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關(guān): 3MHz
電壓/電流 - 輸出 1: 1.5V,800mA
電壓/電流 - 輸出 2: 1.8V,300mA
電壓/電流 - 輸出 3: 3.3V,300mA
帶 LED 驅(qū)動(dòng)器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 20-LFCSP-WQ(4x4)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADP5042ACPZ-2-R7DKR
Data Sheet
ADP5042
 
Rev. A | Page 7 of 32
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Rating
AVIN, VINx, VOUTx, ENx, MODE, MR
, WDIx,
WMOD, WSTAT, nRSTO to GND
0.3 V to +6 V
Storage Temperature Range
65癈 to +150癈
Operating Junction Temperature Range
40癈 to +125癈
Soldering Conditions
JEDEC J-STD-020
ESD Human Body Model
3000 V
ESD Charged Device Model
1500 V
ESD Machine Model
100 V
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP5042 can be damaged when the junction temperature
limits are exceeded. Monitoring ambient temperature does not
guarantee that the junction temperature is within the specified
temperature limits. In applications with high power dissipation
and poor thermal resistance, the maximum ambient
temperature may have to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature can exceed the maximum
limit as long as the junction temperature is within specification
limits. The junction temperature of the device is dependent on
the ambient temperature, the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package. Maximum junction temperature is calculated from the
ambient temperature and power dissipation using the formula
T
J
 = T
A
 + (P
D
 ??/DIV>
JA
)
Junction-to-ambient thermal resistance (?/DIV>
JA
) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of ?SPAN class="pst ADP5042ACPZ-2-R7_2473600_6">JA may vary, depending on
PCB material, layout, and environmental conditions. The specified
value of ?SPAN class="pst ADP5042ACPZ-2-R7_2473600_6">JA is based on a four-layer, 4 ?3 , 2.5 oz copper board,
as per JEDEC standard. For additional information, see the
AN-772 Application Note, A Design and Manufacturing Guide 
for the Lead Frame Chip Scale (LFCSP).
THERMAL RESISTANCE
?/DIV>
JA
 is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type
?/DIV>
JA
 
?/DIV>
JC
 
Unit
20-Lead, 0.5 mm pitch LFCSP
38
4.2
癈/W
 
ESD CAUTION
 
 
 
 
 
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