參數(shù)資料
型號(hào): ADP3502
廠商: Analog Devices, Inc.
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: CDMA Power Management System
中文描述: CDMA的電源管理系統(tǒng)
文件頁數(shù): 25/36頁
文件大?。?/td> 714K
代理商: ADP3502
REV. 0
ADP3502
–25–
In Figure 11
:
Voltage Detect Delay: Voltage Detect Signal (10 ms Delay)
(1: Assert)
Charger detect: Charger Detect Signal (1: Assert)
Alarm INT: Alarm Detect Signal (Alarm 1 or Alarm 2)
(1: Assert)
PWRONKEY–: Power On Key Input (0: Assert)
OPT1–: Power On Signal (0: Assert)
OPT2–: Power On Signal (0: Assert)
OPT3: Power On Signal (1: Assert)
10 ms Delay
This block generates a 10 ms delayed signal after the reset of the
voltage detect signal is released. 10 ms (11 clocks of 1024 Hz) after
the voltage detect signal is asserted, the voltage detect delay
signal is asserted. If the duration of the voltage detect signal is
less than 10 ms, the voltage detect delay signal will not be
asserted. When the voltage detect signal is released, the voltage
detect delay signal is released simultaneously. The voltage detect
delay signal can be reset by writing “1” in the POWER OFF
register (21h).
If users want to go back to a Power ON state, users should set
“1” to address 22h within a time constant of the external R/C
network, which is suppose to be connected to OPT2.
Note that users just need to write a “1” in the Power OFF regis-
ter to reset the voltage detect delay and do not need to overwrite
it with a “0.”
POWERONKEY
POWER ON
POWER ON
POWER OFF
LDO1, LDO2, LDO3,
LDO4, LDO6, LDO11
LDO1b, LDO2b, LDO6b
VOLTAGE DETECTOR
VOLTAGE DETECT DELAY
RSTDELAY–
OPT2
INT–
SERIAL I/F
10ms
50ms
CLEAR INT
CLEAR INT– AND SET PWROFF (21h) = 1
Figure 12. Power ON Sequence
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