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參數(shù)資料
| 型號(hào)： | ADP3502 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | CDMA Power Management System |
| 中文描述： | CDMA的電源管理系統(tǒng) |
| 文件頁數(shù)： | 20/36頁 |
| 文件大?。?/td> | 714K |
| 代理商： | ADP3502 |
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REV. 0
–20–
ADP3502
Adapter Connection
There are two adapter connections on the ADP3502, Pins
ADAPTER and ADPSUPPLY. The ADPSUPPLY pin only
provides bias current to the charger detect comparator and
precharge block. With a diode placed on the adapter side of the
PNP transistor, as shown in Figure 3, the reverse battery current
will be blocked.
Charger Detect Function
The ADP3502 will detect that a charging adapter has been applied
when the voltage at the ADAPTER pin exceeds the voltage at
BVS. The ADAPTER pin voltage must exceed the BVS voltage
by a small positive offset. This offset has hysteresis to prevent
jitter at the detection threshold. The charger detection comparator
will set the charger detect flag in the 20h register and generate
an interrupt to the system. If the ADAPTER input voltage drops
below the detection threshold, charging will stop automatically,
and the charger detect flag will be cleared and generate an
interrupt also.
DDLO Function and Operation
The ADP3502 contains a comparator that will lock out system
operation if the battery voltage drops to the point of deep dis-
charge. When the battery voltage exceeds 2.675 V, the reference
will start as will the sub-LDO3b. If the battery voltage drops
below the hysteresis level, the reference and LDOs will be shut
down if for some reason they are still active. Since LDO1 will be in
deep drop-out and well below the voltage detector threshold at this
point, the reset generator will have already shut down the rest of
the system via RESET+, RESETOUT–, and RSTDELAY–.
If a charging adapter has been applied to the system, the DDLO
comparator will force the charging current to trickle charge if
the battery is below the DDLO threshold. During this time, the
charging current is limited to 5 mA. When the battery voltage
exceeds the upper threshold, the low current charging is enabled,
which allows 55 mV (typical) across the external charge current
sense resistor (see Figure 4).
MVBAT
The ADP3502 provides a scaled buffered output voltage for use
in reading the battery voltage with an A/D converter. The bat-
tery voltage is divided down to be nominally 2.600 V at the
full-scale battery of 4.35 V. To assist with calibrating out system
errors in the ADP3502 and the external A/D converter, this full-
scale voltage may be trimmed digitally with five bits stored in
register 12h. At full-scale input voltage, the output voltage of
MVBAT can be scaled in 6 mV steps, allowing a very fine cali-
bration of the battery voltage measurement. The MVBAT buffer is
enabled by the MVEN bit of register 11h and will consume less
than 1
μ
A of leakage current when disabled.
Reference
The ADP3502 has an internal temperature compensated and
trimmed band gap reference. The battery charger and LDOs all
use this system reference. This reference is not available for use
externally. However, to reduce thermal noise in the LDOs, the
reference voltage is brought out to the NRCAP pin through a
50 k
internal resistor. A cap on the NRCAP pin will complete
a low-pass filter that will reduce the noise on the reference volt-
age. All the LDOs, with the exception of LDO3, use the filtered
reference.
Since the reference voltage appears at NRCAP through a 50 k
series internal impedance, it is very important to never place any
load current on this pin. Even a voltmeter with 10 M
input
impedance will affect the resulting reference voltage by about
6 mV or 7 mV, affecting the accuracy of the LDOs and charger.
If for some reason the reference must be measured, be certain to
use a high impedance range on the voltmeter or a discrete high
impedance buffer prior to the measurement system.
LOGIC BLOCKS
ADP3502 includes the following functions:
3-wire serial interface (CS, CLK, DATA)
RTC counter section has year, month, day, week, hour,
minute, and second and controls leap year and days in month
automatically.
Detect alarms based on RTC counter
Periodically constant interrupt feature (2 Hz, 1 Hz, 1/60 Hz,
1/3600 Hz, once a month)
GPIO and INT ports control
Keypad interface
LED light control
LDO functions
Clock and reset output control
Stay-alive timer
Figure 6 is a block diagram based on the logic circuit.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADP3502ASU | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3502ASU-REEL | 制造商:Analog Devices 功能描述:CDMA Power Management System 64-Pin TQFP T/R |
| ADP3510 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3510ARU | 制造商:AD 制造商全稱:Analog Devices 功能描述:CDMA Power Management System |
| ADP3510ARU-REEL7 | 制造商:Analog Devices 功能描述: |
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