參數(shù)資料
型號: ADN4604ASVZ
廠商: Analog Devices Inc
文件頁數(shù): 8/40頁
文件大?。?/td> 0K
描述: IC CROSSPOINT SWIT 16X16 100TQFP
標(biāo)準(zhǔn)包裝: 1
系列: XStream™
功能: 交叉點開關(guān)
電路: 1 x 16:16
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 2.7 V ~ 3.6 V
電流 - 電源: 95mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
ADN4604
Data Sheet
Rev. A | Page 16 of 40
THEORY OF OPERATION
INTRODUCTION
The ADN4604 is a 16 × 16, buffered, asynchronous crosspoint
switch that provides input equalization, output preemphasis,
and output level programming capabilities. The receivers
integrate an equalizer that is optimized to compensate for
typical backplane losses. The switch supports multicast and
broadcast operation, allowing the ADN4604 to work in
redundancy and port-replication applications. The part offers
extensively programmable output levels and preemphasis
settings.
EQ
RX
TX
PRE-
EMPHASIS
16 × 16
SWITCH
MATRIX
CONNECTION
MAP 0
CONNECTION
MAP 1
SERIAL
INTERFACE
CONTROL
LOGIC
PER-PORT
OUTPUT
LEVEL
SETTINGS
OUTPUT
LEVEL
HOOKUP
TABLE
ADN4604
VCC
VEE
DVCC
OP[15:0]
VTTON,
VTTOS
ON[15:0]
IP[15:0]
VTTIE,
VTTIW
IN[15:0]
I2C/SPI
ADDR1/SDI
SDA/SDO
SCL/SCK
RESET
UPDATE
ADDR0/CS
07934-
039
Figure 39. Block Diagram
The configuration of the crosspoint is controlled through
a serial interface. This interface supports both I2C and SPI
protocols, which can be selected using the I2C /SPI dedicated
control pin. There are two I2C address pins available as
described in Table 6.
Table 6. Serial Interface Control Modes
Pin
No.
I2C/SPI = 0
I2C/SPI = 1
Pin
Name
Pin
Function
Pin
Name
Pin
Function
50
ADDR1
I2C Address
MSB
SDI
SPI Data
Input
51
ADDR0
I2C Address
LSB
CS
SPI Chip
Select
75
SDA
I2C Data
SDO
SPI Data
Output
76
SCL
I2C Clock
SCK
SPI Clock
RECEIVERS
The ADN4604 receiver inputs incorporate 50 Ω termination
resistors, ESD protection, and an equalizer that is optimized for
operation over long backplane traces. Each receive channel also
provides a positive/negative (P/N) inversion function, which allows
the user to swap the sign of the input signal path to eliminate the
need for board-level crossovers in the receiver channel.
VCC
VTTIx
IPx
INx
VEE
SIMPLIFIED RECEIVER INPUT CIRCUIT
RLN
RL
RLP
RL
Q1
Q2
I1
R3
1k
R1
750
R2
750
RN
52
RP
52
07934-
040
Figure 40. Simplified Input Circuit
Equalization
The ADN4604 receiver incorporates a continuous time equalizer
(EQ) that provides 12 dB of high frequency boost to compensate
up to 40 inches of FR4 at 4.25 Gbps. Each input has an equalizer
control bit. By default, the programmable boost is set to 12 dB.
The boost can be set to 0 dB by programming a Logic 0 to the
respective register bit for the corresponding channel.
Table 7. Equalization Control Registers
EQ[15:0]
Equalization Boost
0
0 dB
1
12 dB (default)
Lane Inversion
The receiver P/N inversion is a feature intended to allow the
user to implement the equivalent of a board-level crossover in
a much smaller area and without additional via impedance
discontinuities that degrade the high frequency integrity of the
signal path. The P/N inversion is available independently for
each of the 16 input channels and is controlled by writing to the
SIGN bit of the RX control registers (Addresses 0x12 and
Address 0x13). Note that using this feature to account for signal
inversions downstream of the receiver requires additional
attention when switching connectivity.
Table 8. Signal Path Polarity Control
SIGN[15:0]
Signal Path Polarity
0
Noninverting (default)
1
Inverting
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