
Data Sheet
ADN4604
Rev. A | Page 19 of 40
TRANSMITTERS
The ADN4604 transmitter outputs incorporate 50 Ω termin-
ation resistors, ESD protection, and output current switches.
Each channel provides independent control of both the absolute
output level and the preemphasis output level. Note that the
choice of output level affects the output common-mode level.
ON-CHIP TERMINATION
ESD
VCC
VTTOx
OPx
ONx
VEE
V3
VC
V2
VP
V1
VN
Q1
IT
IDC + IPE
Q2
RP
50
RN
50
079
34-
04
2
Figure 42. Simplified TX Output Circuit
Preemphasis
Transmission line attenuation can be equalized at the trans-
mitter using preemphasis. The transmit equalizer setting can
be chosen by matching the channel loss to the amount of boost
provided by the preemphasis.
Basic Settings
In the basic mode of operation, predefined preemphasis settings
are available through a lookup table. Each table entry requires
two bytes of memory. The amount of preemphasis provided
is independent of the full-scale current output. Transmitter
preemphasis levels, as well as dc output levels, can be set
through the serial control interface. The output level and
amount of preemphasis can be independently programmed
through advanced registers. By default, however, the total
output amplitude and preemphasis setting space is reduced
to a single table of basic settings that provides eight levels of
output equalization to ease programming for typical FR4
channels.
Table 10 summarizes the absolute output level, preemphasis
level, and high frequency boost for control setting. The full
resolution of eight settings is available through the serial
interface by writing to Bits[2:0] (the TX PE[2:0] bits) of the
Basic TX Control registers shown
in Table 11. A single setting
is programmed to all outputs simultaneously by writing to the
0x18 broadcast address.
The TX has four possible output enable states (disabled,
standby, squelched, and enabled) controlled by the TX EN[1:0]
bits as shown
in Table 11. Disabled is the lowest power-down
state. When squelched, the output voltage at both P and N
outputs will be the common-mode voltage as defined by the
output current settings. In standby, the output level of both P
and N outputs will be pulled up to the termination supply
(VTTON or VTTOS).
The TX CTL SELECT bit (Bit 6) in the TX[15:0] basic control
register determines whether the preemphasis and output
current controls for the channel of interest are selected from
the predefined lookup table or directly from the TX[15:0]
illustration of the TX control circuit. Setting the TX CTL
SELECT bit low (default setting) selects preemphasis control
from the predefined, optimized lookup table (Address 0x60
to Address 0x6F).
07
93
4-
04
3
TABLE
ENTRY 0
TABLE
ENTRY 1
TABLE
ENTRY 2
TABLE
ENTRY 3
TABLE
ENTRY 4
TABLE
ENTRY 5
TABLE
ENTRY 6
TABLE
ENTRY 7
16
3
PE[2:0]
TX CTL
SELECT
IPx
OPx
INx
ONx
TX
PER OUTPUT PORT
LOOKUP TABLE
BASIC SETTINGS
PER PORT
OUTPUT LEVEL
ADVANCED SETTINGS
TX EN[1:0]
2
Figure 43. Transmitter Control Block Diagram
In applications where the default preemphasis settings in the
lookup table are not sufficient, the lookup table entries can be
modified by programming the TX lookup table registers (0x60
table entries are insufficient, each output can be programmed
individually.
Table 10. Preemphasis Boost and Overshoot vs. Setting
PE
Setting
Main Tap
Current
(mA)
Delayed Tap
Current (mA)
Boost
(dB)
Overshoot
(%)
DC Swing
(mV p-p)
0
16
0
0.0
0
800
1
16
2
2.0
25
800
2
16
5
4.2
62.5
800
3
16
8
6.0
100
800
4
11
8
7.8
145
550
5
8
9.5
200
400
6
4
6
12.0
300
7
4
6
12.0
300