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參數(shù)資料
| 型號： | ADN4600ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH 8X8 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點開關(guān) |
| 電路： | 1 x 8:8 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.7 V ~ 3.6 V |
| 電流 - 電源： | 460mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADN4600ACPZ-R7DKR |
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ADN4600
Data Sheet
Rev. A | Page 24 of 28
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance. The exposed pad should be connected to the VEE
plane using plugged vias so that solder does not leak through
the vias during reflow.
Use of a 10 F electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. It is recommended that 0.1 F and 1 nF ceramic chip
capacitors be placed in parallel at each supply pin for high
frequency power supply decoupling. When using 0.1 F and 1 nF
ceramic chip capacitors, they should be placed between the IC
power supply pins (VCC, VTTI, VTTO) and VEE, as close as
possible to the supply pins.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be attained by using close spacing
between the planes. This capacitance is given by
CPLANE = 0.88εr A/d (pF)
where:
ε
r is the dielectric constant of the PCB material.
A is the area of the overlap of power and GND planes (cm2).
d is the separation between planes (mm).
For FR4, εr = 4.4 and 0.25 mm spacing, C ~15 pF/cm2.
Transmission Lines
Use of 50 transmission lines is required for all high frequency
input and output signals to minimize reflections. It is also necessary
for the high speed pairs of differential input traces, as well as the
high speed pairs of differential output traces, to be matched in
length to avoid skew between the differential traces.
Soldering Guidelines for Chip Scale Package
The lands on the LFCSP are rectangular. The printed circuit
board pad for these should be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land should be centered on the pad. This ensures that the
solder joint size is maximized. The bottom of the chip scale
package has a central exposed pad. The pad on the printed
circuit board should be at least as large as this exposed pad. The
user must connect the exposed pad to VEE using plugged vias
so that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
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| ADN4600-EVALZ | 制造商:Analog Devices 功能描述:Development Kit For ADN4600 4.25 Gbps, 8 X 8, Asynchronous Nchronous Crosspoint Switch 制造商:Analog Devices 功能描述:EVALUATION BOARD - Boxed Product (Development Kits) |
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| ADN4604ASVZ | 功能描述:IC CROSSPOINT SWIT 16X16 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:XStream™ 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤 |
| ADN4604ASVZ-RL | 功能描述:IC CROSSPOINT SWIT 16X16 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:XStream™ 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
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