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參數(shù)資料
| 型號： | ADN4600ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SWITCH 8X8 64LFCSP |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點開關 |
| 電路： | 1 x 8:8 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.7 V ~ 3.6 V |
| 電流 - 電源： | 460mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 標準包裝 |
| 其它名稱： | ADN4600ACPZ-R7DKR |
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Data Sheet
ADN4600
Rev. A | Page 23 of 28
I2C Interface Data Transfers: Data Read
To read data from the ADN4600 register set, a microcontroller
(or any other I2C master) needs to send the appropriate control
signals to the ADN4600 slave device. Use the following steps,
where the signals are controlled by the I2C master unless otherwise
specified. A diagram of the procedure is shown in Figure 32.
1.
Send a start condition (that is, while holding the SCL line
high, pull the SDA line low).
2.
Send the ADN4600 part address (seven bits), whose upper
five bits are the static value b10010 and whose lower two
bits are controlled by the ADDR1 and ADDR0 input pins.
This transfer should be MSB first.
3.
Send the write indicator bit (0).
4.
Wait for the ADN4600 to acknowledge the request.
5.
Send the register address (eight bits) from which data is to
be read. This transfer should be MSB first. The register
address is kept in the ADN4600 memory until the part is
reset or the register address is written over with the same
procedure (Step 1 to Step 6 of the write procedure; see the
I2C Interface Data Transfers: Data Write section).
6.
Wait for the ADN4600 to acknowledge the request.
7.
Send a repeated start condition (that is, while holding the
SCL line high, pull the SDA line low).
8.
Send the ADN4600 part address (seven bits), whose upper
five bits are the static value b10010 and whose lower two
bits are controlled by the ADDR1 and ADDR0 input pins.
This transfer should be MSB first.
9.
Send the read indicator bit (1).
10. Wait for the ADN4600 to acknowledge the request.
11. The ADN4600 then serially transfers the data (eight bits) held
in the register indicated by the address set in Step 5.
12. Acknowledge the data.
13. Send a stop condition (that is, while holding the SCL line
high, pull the SDA line high) and release control of the bus.
14. Send a repeated start condition (that is, while holding the
SCL line high, pull the SDA line low) and continue with
Step 2 of the write procedure (see the I2C Interface Data
Transfers: Data Write section) to perform a write.
15. Send a repeated start condition (that is, while holding the
SCL line high, pull the SDA line low) and continue with
Step 2 of the read procedure to perform a read from a
another address.
16. Send a repeated start condition (that is, while holding the
SCL line high, pull the SDA line low) and continue with
Step 8 of the read procedure to perform a read from the
same address.
In Figure 32, the ADN4600 read process is shown. The SCL
signal is shown, along with a general read operation and a
specific example. In the example, Data 0x49 is read from Register
Address 0x6D of an ADN4600 part with a slave address of 0x4B.
The part address is seven bits wide. The upper five bits of the
slave address are internally set to b10010. The lower two bits
are controlled by the ADDR[1:0] pins. In this example, the bits
controlled by the ADDR[1:0] pins are set to b11. In Figure 32,
the corresponding step number is visible in the circle under the
waveform. The SCL line is driven by the I2C master, not by the
ADN4600 slave. As for the SDA line, the data in the shaded
polygons of Figure 32 is driven by the ADN4600, whereas the
data in the nonshaded polygons is driven by the I2C master. The
end phase case shown corresponds with Step 13.
It is important to note that the SDA line only changes when
the SCL line is low, except when a start, stop, or repeated start
condition is being sent, as is the case in Step 1, Step 7, and Step 13.
In Figure 32, Sr represents a repeated start where the SDA line
is brought high before SCL is raised. SDA is then dropped while
SCL is still high.
3
2
1
SCL
SDA
GENERAL CASE
EXAMPLE
4
5
6
7
8
10
9
8
11
12
13
07
06
1-
00
9
START
REGISTER ADDR
AA
ASr
A
STOP
DATA
FIXED PART
ADDR
FIXED PART
ADDR
[1:0]
ADDR
[1:0]
R/
W
R/
W
NOTES
1. A = ACK.
2. Sr = A REPEATED START WHERE THE SDA LINE IS BROUGHT HIGH BEFORE SCL IS RAISED.
Figure 32. I2C Read Diagram
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