參數(shù)資料
型號: ADN4600ACPZ-R7
廠商: Analog Devices Inc
文件頁數(shù): 14/28頁
文件大?。?/td> 0K
描述: IC CROSSPOINT SWITCH 8X8 64LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: XStream™
功能: 交叉點(diǎn)開關(guān)
電路: 1 x 8:8
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.7 V ~ 3.6 V
電流 - 電源: 460mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADN4600ACPZ-R7DKR
Data Sheet
ADN4600
Rev. A | Page 21 of 28
Selective Squelch and Disable
Each transmitter is equipped with disable and squelch controls.
Disable is a full power-down state: all transmitter current,
including output current, is reduced to 0 mA and the output
pins are pulled up to VTTO, but there is a delay of
approximately 1 s associated with re-enabling the transmitter.
The output disable control is accessed through the TX EN bit
(Bit 5) of the TX[7:0] configuration registers through the I2C
control interface.
Squelch simply reduces the output current to submicroamp
levels, allowing both output pins to pull up to VTTO through
the output termination resistors. The transmitter recovers from
squelch in less than 100 ns.
The output squelch and the output disable control can both be
accessed through the TX[7:0] squelch control registers, with the
top nibble representing the squelch control and the bottom nibble
representing the output disable for one channel. The channels
are disabled or squelched by writing 0s to the corresponding
nibbles. The channels are enabled by writing all 1s, which is the
default setting. For example, to squelch channel TX0, Register
0xC3 must be set to 0x0F. The entire nibble must be written to
all 0s for this functionality.
Table 15. Transmitters Squelch Control Registers
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
TX[7:0] Squelch Control
0xE3, 0xEB,
0xF3, 0xFB,
0xDB, 0xD3,
0xCB, 0xC3
SQUELCHb[3:0]
DISABLEb[3:0]
0xFF
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