I2C CONTROL INTERFACE Serial Interface" />
參數(shù)資料
型號(hào)： ADN4600ACPZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/28頁(yè)
文件大小： 0K
描述： IC CROSSPOINT SWITCH 8X8 64LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： XStream™
功能： 交叉點(diǎn)開關(guān)
電路： 1 x 8:8
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 1.7 V ~ 3.6 V
電流 - 電源： 460mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： ADN4600ACPZ-R7DKR
ADN4600
Data Sheet
Rev. A | Page 22 of 28
I2C CONTROL INTERFACE
Serial Interface General Functionality
The ADN4600 register set is controlled through a 2-wire I2C
interface. The ADN4600 acts only as an I2C slave device. Therefore,
the I2C bus in the system needs to include an I2C master to
configure the ADN4600 and other I2C devices that may be on
the bus. Data transfers are controlled by the two I2C wires: the
SCL input clock pin and the SDA bidirectional data pin.
The ADN4600 I2C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line only changes value
when the SCL pin is low, with two exceptions: the SDA pin is
driven low while the SCL pin is high to indicate the beginning
or continuation of a transfer, and the SDA line is driven high
while the SCL line is high to indicate the end of a transfer.
Therefore, it is important to control the SCL clock to toggle
only when the SDA line is stable, unless indicating a start,
repeated start, or stop condition.
I2C Interface Data Transfers: Data Write
To write data to the ADN4600 register set, a microcontroller
(or any other I2C master) needs to send the appropriate control
signals to the ADN4600 slave device. Use the following steps,
where the signals are controlled by the I2C master unless otherwise
specified. A diagram of the procedure is shown in Figure 31.
1.
Send a start condition (that is, while holding the SCL line
high, pull the SDA line low).
2.
Send the ADN4600 part address (seven bits), whose upper
five bits are the static value b10010 and whose lower two
bits are controlled by the ADDR1 and ADDR0 input pins.
This transfer should be MSB first.
3.
Send the write indicator bit (0).
4.
Wait for the ADN4600 to acknowledge the request.
5.
Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
6.
Wait for the ADN4600 to acknowledge the request.
7.
Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
8.
Wait for the ADN4600 to acknowledge the request.
9.
Send a stop condition (that is, while holding the SCL line
high, pull the SDA line high) and release control of the bus.
10. Send a repeated start condition (that is, while holding the
SCL line high, pull the SDA line low) and continue with
Step 2 in this procedure to perform another write.
11. Send a repeated start condition (that is, while holding the
SCL line high, pull the SDA line low) and continue with
Step 2 of the read procedure (see the I2C Interface Data
Transfers: Data Read section) to perform a read from
another address.
12. Send a repeated start condition (that is, while holding the
SCL line high, pull the SDA line low) and continue with
Step 8 of the read procedure (in the I2C Interface Data
Transfers: Data Read section) to perform a read from the
same address set in Step 5 of the write procedure.
In Figure 31, the ADN4600 write process is shown. The SCL
signal is shown, along with a general write operation and a
specific example. In the example, Data 0x92 is written to Register
Address 0x6D of an ADN4600 part with a slave address of 0x4B.
The slave address is seven bits wide. The upper five bits of the
slave address are internally set to b10010. The lower two bits
are controlled by the ADDR[1:0] pins. In this example, the bits
controlled by the ADDR[1:0] pins are set to b11. In the figure,
the corresponding step number is visible in the circle under the
waveform. The SCL line is driven by the I2C master, not by the
ADN4600 slave. As for the SDA line, the data in the shaded
polygons of Figure 31 is driven by the ADN4600, whereas the
data in the nonshaded polygons is driven by the I2C master. The
end phase case shown corresponds with Step 9.
It is important to note that the SDA line only changes when
the SCL line is low, except when a start, stop, or repeated start
condition is being sent, as is the case in Step 1 and Step 9.
1
SCL
SDA
GENERAL CASE
EXAMPLE
START
REGISTER ADDR
ACK
STOP
DATA
R/W
FIXED PART ADDR
ADDR
[1:0]
2
3
4
5
6
7
8
9
0
70
61
-0
08
Figure 31. I2C Write Diagram
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